β-Ga₂O₃ is an ultrawide bandgap semiconductor with attractive properties for high-power electronics including a high theoretical breakdown field of 8 MV/cm and availability of melt-grown substrates. Low room-temperature electron mobility and low thermal conductivity result in both high sheet-resistance and high thermal resistance, limiting field-effect transistor performance. A ‘fin’ channel structure can overcome these challenges by utilizing a tri-gate geometry to enable electrostatic control over a high sheet-charge density channel while also providing additional surface area for thermal management in the active region. A key process technology for non-planar devices is a low-damage etch method. In this work, we demonstrate β-Ga₂O₃ lateral FinFETs with high sheet charge density fabricated with a novel damage-free atomic Ga flux etching technique [N.K. Kalarickal et al. APL 119 (2021)]. The epitaxial structure was grown by MOCVD on a (010) Fe-doped semi-insulating substrate. An Mg-doped layer was used to compensate Si donors at the substrate-growth interface to eliminate any parasitic channel. A 500 nm buffer layer was used to isolate the 600 nm Si-doped channel from the Mg and Fe dopants. The process flow started with selective-area MOCVD regrowth of n+ source/drain using a PECVD SiO₂ mask patterned by optical lithography and dry etching. Then a SiO₂ mask for the fins and mesa isolation layer was patterned by electron-beam and optical lithography. The sample was etched by atomic Ga flux ­in an MBE chamber. Electron-beam evaporated Ti/Au ohmic contacts were annealed in an N₂ ambient. Ni gates were deposited by RF sputtering. Hall measurements revealed a sheet-charge density of 2.28x10¹³ cm^-2, a mobility of 134 cm²/V.s and a sheet resistance of 1.77 kΩ/sq. Transfer length method showed a contact resistance of 1.27 Ω.mm, a sheet resistance of 2.03 kΩ/sq and a specific contact resistivity of 9.11x10^-6 Ω.cm². C-V measurements at 100 KHz were used to extract a doping density of 6x10¹⁷ cm^-3 in the channel. Current density is above 250 mA/mm normalized to the total fin width for a device with a gate length of 1.5 µm and an L_SD of 2.5 µm. Transfer characteristics show a threshold voltage of -12 V for a fin width of 200 nm. The on/off ratio of 10⁵ is limited by the reverse leakage of the Schottky gate. In summary, β-Ga₂O₃ FinFETs with scaled fins were fabricated using novel damage-free Ga flux etching and show promising electrical performance. We acknowledge funding from DOE/NNSA under Award Number(s) DE-NA000392 and AFOSR GAME MURI (Award No. FA9550-18-1-0479, project manager Dr. Ali Sayir).

Off-state leakage currents in lateral Ga₂O₃ FET devices have previously been attributed to the presence of unintentional Si (n-type) at the interface between epitaxial grown layer and the substrate [1-4], i.e., a parallel leakage conducting channel. High Fe-doping (>10¹⁹ cm^-3) at the surface of the Ga₂O₃ substrate, followed by thermal annealing, has been shown to compensate the unintentional Si impurities, thereby reducing the leakage current. However, elevated off-state currents and low on-off ratios have still been observed in these devices [4]. Here, we utilize electrical characterization and TCAD simulations to explore the behaviour of leakage current due to Si impurities at the surface of the substrate in lateral Ga₂O₃ transistors.

Lateral Ga₂O₃ transistors studied here were processed on an MBE-grown epitaxial layer on surface-implanted (Fe, p-type) semi-insulating Ga₂O₃ substrates, followed by thermal annealing (more details in ref. 4). The transfer characteristic reveals a pinch-off current (10^-7A/mm) with an insensitivity to the gate voltage (Fig 2(a)). The pinch-off current demonstrates ohmic characteristics under opposite drain voltage. The clockwise hysteresis in the C-V and the depletion width (Fig 3) indicate a donor-like trapping effect located near the epitaxy/substrate interface with an activation energy of 0.5eV determined by drain current transients (Fig 4).

2D TCAD simulations (Fig 5), using the SIMS profile for Fe and Si [4] as input parameters, illustrate that the residual Si at the epitaxy/substrate interface pin the Fermi level near the conduction band, resulting in the formation of a parallel conducting channel at the epitaxy/substrate interface (Fig 5(b)). Electrons, from the traps in the epilayer and the contacts, travel vertically to the parallel channel at that interface under negative gate bias. The insensitivity of the leakage current to the gate voltage can be explained by the pinning of the Fermi level due to the high concentration of residual Si dopants. The leakage current magnitude is mostly governed by the resistance of the UID Ga₂O₃ rather than the parallel conduction channel. The latter is evidenced by the constant resistance of the parallel channel in set of circular isolation structures with different spacing (Fig.6). An activation energy of 0.36eV was determined for the leakage current pathway, which contains contributions from the UID layer and the parallel channel (Fig. 7). The mechanism discussed here highlights the role of residual Si contaminants on leakage current. Reduction in their concentration or full compensation is crucial for enhancing performance and device design respectively.

The dynamic switching loss figure of merit (R_ONQ_G vs. V_BK) is a benchmark used to indicate a device’s potential in power-switching applications. Similarly, the lateral Power Figure of Merit (R_ON,sp vs. V_BK) indicates a devices conduction losses.. This work discusses the fabrication and FOM characterization of optical gate and EBL gate Ga₂O₃ MOSFETs and shows their potential for these application spaces that are currently dominated by other technologies.

A 50 nm Si doped β-Ga₂O₃ channel layer was homoepitaxially grown on a Fe doped (010) substrate by ozone molecular beam epitaxy (MBE) targeting 1.0x10¹⁸ cm^-3 carrier concentration. Device fabrication began with mesa isolation using a high-power BCl₃/Cl₂ ICP etch. Contact to the active layer was achieved with a Ti/Al/Ni/Au metal stack deposited by electron beam metal evaporation followed by a 470 ºC anneal in N₂ ambient for 2 minutes. 20 nm of Al₂O₃ gate dielectric was deposited via plasma-enhanced atomic layer deposition. Optical I-gate contacts were defined on half of the sample via optical stepper lithography followed by Ni/Au metal evaporation. Scaled gamma-gates were defined on the remaining half via electron-beam lithography followed by Ni/Au metal evaporation. Interconnect metal was defined via stepper lithography followed by Ti/Au metal evaporation.

Gate capacitance was collected as a function of gate voltage at a frequency of 1 MHz, and can be seen for the various device types in Figures 2 A and B. Integration over the collected gate voltage range produces the experimentally extracted Q_GS of .0014/.0011 and .00082/.00078 nC for the optical and e-beam gate devices respectively. Q_GD is calculated assuming maximum depletion of the entire L_GD, Using the equation Q = qN_DAT. This provides a conservative representation of the total gate charge for these devices when Q_G = Q_GS + Q_GD of .0060/.0041 nC and .0050/.0034 nC for optical and EBL gate devices respectively. Standard DC I-V device characterization was performed and is shown in Figure 3(A-F).

Beyond the extensive literature on the properties and applications of β-Ga₂O₃ for high power devices, the effects of strong electric fields on the Ga₂O₃ microstructure and in particular the impact of electrically active native point defects have been relatively unexplored.We used cathodoluminescence (CL) point spectra and hyperspectral imaging to observe the spatial rearrangement of oxygen vacancy and vacancy-related defects in Ga₂O₃ vertical trench devices under strong reverse bias.The low crystal symmetry of β-Ga₂O₃ leads to unequal migration of V_O and H-related defects under applied bias resulting in a preferential accumulation of donor species near trench corners where the applied field is strongest, increasing the electric field locally and likely leading to breakdown of the dielectric region.Point defect redistribution along the biasing direction demonstrate post-operando the reduced surface electric field (RESURF) effect modulated by the device geometry.

We used CL point spectra and HSI mapping to demonstrate how point defect related donor species in β-Ga₂O₃ vertical Schottky diodes migrate and redistribute under high reverse electrical bias.The accumulation of donor-related defects at Schottky barrier trench corners increases the local doping density and decreases the Ga₂O₃ depletion width such that the electric field falls across a narrower total insulator region, thereby increasing the field locally in the nanoscale trench corner.The low crystal symmetry of the monoclinic crystal structure results in unequal migration energies for point defects on inequivalent lattice sites and along inequivalent crystallographic directions, suggesting a preferential migration of specific three-fold coordinated oxygen vacancies and/or migration of positively charged hydrogen species, altering the relative intensity of the UV emissions that we observe via spatially resolved CL maps and linecuts.Together with the local electrical field maximum under reverse bias resulting from the fin/trench design, this local doping increase due to defect migration suggests a point-of-failure near the trench corners. More generally, defect migration and local doping changes under extreme electric fields in β-Ga₂O₃ demonstrates the potential impact of nanoscale device geometry in other high-power semiconductor device structures.

This work supported by AFOSR grant FA9550-18-1-0066 and NSF grant DMR-18-00130.This work also supported by AFOSR under Grant FA9550-18-1-0529 and made use of the Cornell Center for Materials Research Facilities supported by NSF MRSEC program (DMR-1719875).