ALD/ALE 2025 Session AA1-TuM: Memory Applications II

HfO₂-based ferroelectric memory (FeRAM) has emerged as a promising candidate for next-generation nonvolatile memories, owing to its remarkable compatibility with CMOS processes and scalability. However, the reliability of HfO₂-based materials remains a significant challenge, primarily due to their limited endurance and easy dielectric breakdown. These issues can be attributed to their large coercive field, which not only increases the operating voltage but also enhances the risk of dielectric breakdown. In this work, Ga-doped HfO₂ ferroelectric capacitors with varying concentrations and annealing temperatures are prepared by atomic layer deposition (ALD) technique for the first time, and their ferroelectric properties, crystal structure, polarization switching kinetics, and endurance characteristics have been systematically investigated. The results indicate that the Ga-doped HfO₂ ferroelectric films exhibit finely modulated coercive fields (E_c) ranging from 1.1 MV/cm (HfO₂/Ga₂O₃ = 32:1) to a very low 0.6 MV/cm (HfO₂/Ga₂O₃ = 11:1). Notably, under 650°C rapid thermal annealing, the W/Ga:HfO₂/W capacitors achieve a comprehensively good ferroelectricity, including a large remnant polarization (2P_r) of 32.0 µC/cm² and a small coercive electric field (E_c) of 0.8 MV/cm. Moreover, the capacitors exhibit robust breakdown reliability, including high breakdown electric field (E_BD, >4.5 MV/cm), large breakdown voltage (>2.7 V) for ten-year time-dependent dielectric breakdown (TDDB) lifetime, and surpassing endurance (>10¹⁰ cycles). The study introduces Ga doping as a viable strategy to enhance the reliability of HfO₂-based FeRAM.

*Corresponding Author: honglianglu@fudan.edu.cn

In recent years, storage class memory (SCM) has been considered as a promising next-generation memory technology, combining fast data processing speed of dynamic random access memory (DRAM) with the non-volatility of NAND flash memory. Among SCMs, ovonic threshold switch (OTS) material-based selector-only memory (SOM) has emerged as a pivotal memory technique, presenting outstanding device performances in terms of power consumption, operational speed, and cycling endurance [1]. In addition, owing to the dual functionality (simultaneous memory and selector operation) of OTS material, its simple memory cell structure exhibits superior scalability, offering cost-effectiveness [2].

To meet the ever-increasing demands for lower fabrication cost and higher memory density, however, it is mandatory to devise vertical SOM based on three-dimensional vertical cross point (3DVXP) array structure. To fabricate vertical SOM devices, thin film deposition technique that guarantees conformal deposition of thin films on high aspect ratio structure is required. In this context, atomic layer deposition (ALD) is a promising thin film deposition technique for the realization of the vertical SOM devices.

In this study, Ge-Sb-Se ternary alloy was synthesized by supercycle ALD process using methanol as co-reactant to enhance the reactivity of precursors. ALD Ge-Sb-Se served as a dual functional material for the memory cell of SOM devices. The material properties of ALD Ge-Sb-Se were thoroughly investigated using various measurement tools. Controlling the sub-cycle ratio during supercycle ALD process, we were able to precisely control the chemical composition of Ge-Sb-Se ternary alloy and determine the optimal composition for the vertical SOM devices. Fabricated SOM devices exhibited average threshold voltage of 2.37 V and average memory window of 1.04 V. Our research results suggest ALD Ge-Sb-Se ternary alloy as an outstanding memory cell component for the next-generation vertical SOM technology.

Acknowledgement

This work was supported by Samsung Electronics.

References

[1] Ravsher, Taras, et al. IEEE Transactions on Electron Devices 70.5 (2023): 2276-2281.

[2] Sung, Ha‐Jun, et al. Advanced Science 11.44 (2024): 2408028.

Effective work function (EWF) tuning through dipole engineering is crucial for enabling multi-Vt options in advanced logic devices such as Gate-All-Around (GAA) nanosheets and Complementary-FET (CFET). The dipole-first approach is one of the most promising candidates for enabling multi-Vt engineering in next-generation logic devices. However, a primary challenge in this scheme is achieving precise Vt fine-tuning [1]. To address this, advanced shifter materials must provide fine-tunable EWF modulation to support diverse Vt flavors. In this study, Y₂O₃ was utilized as a dipole material to enable fine-tunable EWF modulation, while Fluorine Surface Treatment (FST) was applied to passivate defects in the high-k layer to improve electrical performance. Y₂O₃ exhibits strong resistance to fluorine-containing plasma, which prevents IL/channel degradation caused by fluorine plasma incorporation [2].

In this work, nMOS capacitors were fabricated to evaluate V_FB shift and electrical characteristics in dipole-first gate stack. By modulating the thickness of ultra-thin lanthanide oxide films (La₂O₃, Y₂O₃) from 2 Å to 4 Å using atomic layer deposition (ALD). As shown in Fig. 1, V_FB reduction of pristine and fluorine-treated Y₂O₃ at 4 Å was observed at 200mV and 330mV, respectively. In contrast, La₂O₃ at 4 Å exhibited a large V_FB negative shift of 635mV, indicating a significantly broader tuning range. These results demonstrate that Y₂O₃ offers improved EWF fine-tunability, making it a more beneficial alternative to La₂O₃ in dipole-first gate stack. I-V characteristics show a consistent reduction with increasing thickness up to 4 Å for pristine Y₂O₃, whereas La₂O₃ exhibited a decrease only up to 3 Å, followed by an increase at 4 Å. This increase is attributed to IL regrowth and sub-oxide formation, potentially affecting the interfacial properties. Fluorine treated Y₂O₃ shows over an order of magnitude reduction in leakage current compared to pristine Y₂O₃ as shown Fig. 2. The improvement results from defect passivation within the high-k layer, particularly oxygen vacancies, while the strong resistance of Y₂O₃ to fluorine containing plasma helps prevent IL/channel degradation caused by fluorine incorporation.

Our results show that Y₂O₃ exhibits greater potential for fine-tuning compared to La₂O₃, while FST Y₂O₃ also showed improved electrical performance by maintaining a controlled negative V_FB shift with reduced leakage current. Our findings suggest that Y₂O₃ is a promising alternative dipole material for matching the threshold voltage requirements of next-generation advance logic devices such as a CFET architectures.

In-memory computing approaches using memristor crossbars have been proposed as a paradigm shift to overcome the von Neumann bottleneck by combining memory and processing functions. Memristors are considered one of the most promising devices for in-memory computation due to their low power consumption, high switching speed, and scalability. However, sneak paths and stochastic behavior are two critical issues that limit their practical implementation. There have been transformative designs of in-memory computing using either stochasticity or sneak paths, but the combined potential of memristor crossbars remains unexplored. Here we propose a graphlet computing platform that synergistically utilizes both phenomena using a tunable hybrid memristor with a bilayer of insulator fabricated via plasma-enhanced atomic layer deposition (PEALD). By controlling the O₂ plasma power of PEALD, two oxide layers have different oxygen vacancy concentrations that allow for tunable switching behaviors under different switching conditions (Fig. 1). The tunable memristor was integrated into a crossbar, which was used to map a graph by assigning each device as either a node or an edge. Then, we performed graphlet computing by utilizing inherent sneak paths and stochastic behavior of the crossbar (Fig. 2). While the sneak paths are used to count graphlet structures for analyzing complex graphs, the stochasticity is implemented in a random walk process to efficiently solve computationally expensive problems. This newly proposed computing scheme demonstrates the advancement of memristor-based in-memory computing hardware by addressing the inherent issues of memristor technology.

In the advancement of semiconductor device fabrication, integrating high-κ dielectrics and metal electrodes is essential to overcome the limitations of traditional silicon-based MOSFETs. Titanium nitride (TiN) is a pivotal material, effectively mitigating diffusion-induced oxidation at polycrystalline silicon electrode interfaces. TiN have metallic properties like low resistivity and exceptional physical and chemical stability, render it indispensable in applications such as electrodes, surface coatings, and diffusion barriers. Work function of metal electrodes critically influences MOSFET electrical characteristics, including threshold voltage and leakage current. However, Fermi-level pinning in high-κ materials leads to deviations from intrinsic work function values, necessitating the consideration of effective work function values. For TiN, the effective work function typically ranges between 4.6 and 4.8 eV, aligning well with p-MOSFET. In contrast, n-MOSFET require lower work function values, prompting extensive research into methods for reducing TiN's work function to meet these requirements. Atomic layer deposition (ALD) has emerged as a cornerstone technique in semiconductor shrinking, offering unparalleled control over film thickness and composition. TiN thin films are commonly deposited via thermal ALD processes utilizing precursors such as titanium tetrachloride (TiCl₄) and ammonia (NH₃). This approach reliably yields high-quality films with low resistivity. However, the incorporation of chlorine residues necessitates post-deposition at temperatures exceeding 400 °C. Alternatively, metal-organic precursors like tetrakis(dimethylamido)titanium (TDMAT) can be employed; nevertheless, achieving low resistivity with TDMAT often requires plasma-enhanced processes or subsequent high-temperature annealing. In this study, we developed a thermal ALD process using TDMAT and NH₃ as precursors, incorporating trimethylaluminum (TMA) cycles to deposit TiAlCN thin films at a relatively low temperature of 300 °C. This method achieved films with a resistivity of approximately 5000 μΩ·cm, lower than previously reported values for thermal ALD TiN films deposited from TDMAT without post-deposition annealing. Furthermore, by doping aluminum concentrations below 10%, we successfully tuned the work function from 4.9 eV to 4.5 eV. Compared to conventional TiCl₄-based processes, our method offers advantages including reduced carbon contamination and lower deposition temperatures, thereby minimizing potential adverse effects on adjacent thin films. This makes the process particularly suitable for the fabrication of MOSFETs with increasingly complex architectures.

As the demand for continuous miniaturization in semiconductors increases, the search for new interconnect materials has become a key area of innovation. Conventional materials such as copper (Cu) face challenges related to increased resistivity, electron mobility limitations, and electromigration issues [1]. In addition, modern semiconductor processes impose stringent requirements on thermal stability, process compatibility, and interconnect reliability. Against this backdrop, molybdenum (Mo) and ruthenium (Ru) have emerged as promising candidates for next-generation interconnect materials [2]. Their high thermal stability, adaptability to ultrathin film deposition, and compatibility with advanced fabrication environments suggest the potential for a paradigm shift in interconnect design.

Mo and Ru have similar atomic radii, which minimizes lattice distortion when alloyed, thereby suppressing the increase in electrical resistivity [3]. Furthermore, the combination of Mo’s superior oxidation resistance and Ru’s ability to address barrier layer challenges enhances the reliability of interconnect structures. However, successfully integrating MoRu alloys into semiconductor interconnect technology requires reconsideration of nanoscale deposition techniques, including precise thickness control and uniform deposition on high-aspect-ratio structures. To address these challenges, plasma-enhanced atomic layer deposition (PE-ALD) plays a crucial role. Compared to conventional thermal ALD, PE-ALD provides additional reaction energy, enhancing surface reactivity and enabling deposition at lower temperatures, making it particularly suitable for back-end-of-line (BEOL) applications.

In this study, we employ PE-ALD to deposit MoRu thin films, investigating the control of alloy composition, grain growth mechanisms under plasma conditions, and the effect of plasma on film crystallinity. Furthermore, we evaluate the electrical resistivity of the films and conduct reliability tests under high-temperature annealing and current stress conditions. Mo films deposited by ALD exhibited a resistivity of 1167 µΩ·cm at 2 nm and 146 µΩ·cm at 8 nm, while Ru demonstrated an excellent resistivity of 20 µΩ·cm at 7 nm (Fig. 2). To investigate the size effect behavior, an MoRu alloy was fabricated and analyzed. By optimizing the deposition process and material properties, this study aims to assess the feasibility of MoRu as a viable alternative to Cu and W-based interconnects and provide fundamental data for its potential industrial implementation in future semiconductor manufacturing.