ICMCTF2003 Session H2-2: New Materials and Integration Strategies for Future Microdevices

Thursday, May 1, 2003 1:30 PM in Room San Diego

Thursday Afternoon

Time Period ThA Sessions | Abstract Timeline | Topic H Sessions | Time Periods | Topics | ICMCTF2003 Schedule

Start Invited? Item
1:30 PM H2-2-1 High Quality R.F. Sputtered Metal Oxides (Ta, Hf) and their Properties after Annealing
H. Grueger, C. Kunath, E. Kurth, S. Sorge (Fraunhofer IMS, Germany); T. Pechstein (Endress + Hauser Conducta, Germany)
Transition metal oxides are often used as surface coating, dielectric material and for sensor applications, due to their electrical, mechanical and optical properties. The chemical inertness and mechanical resistively along with suitable deposition possibilities lead to wide spread applications. The material properties are known to be dependant on the deposition process and the treatment after deposition. Tantalumpentoxide and hafnium oxide layers have been deposited by r.f. sputtering of high purity targets (99.997 % and higher) on 150 mm oxidized silicon wafers. Typical film thicknesses were 100 nm to 150 nm. The deposition process parameters such as plasma power, pressure, argon/oxygen ratio, gas flow and substrate to target distance have been varied. The substrate holder was held at room temperature during deposition. All layers were amorphous after deposition. The treatment of the layers in pure oxygen and annealing in argon or nitrogen have been studied. Both, process temperature and heating/cooling ramps, have been varied. Rapid thermal processing (RTP) with about 50 K/min ramps and oven processes with about 3 to 3.5 K/min ramps have been used. The layers have been characterized optically by ellipsometry, the surface by SEM and AFM, microstructure by TEM, XPS and AES in cross section. Chemical and electrochemical properties have been measured on specimen in the chemical lab. A high influence of the oxidation and annealing regime have been found. The crystalline structure and accordingly the properties like the chemical stability change significantly. Interesting results have been found with the temperature slope during the annealing process. The heating up time has a very high influence on the structure. Both oxides are compared regarding chemical stability and sensing properties in order to estimate the usability in various sensor applications.
2:10 PM H2-2-3 Pulsed Laser Deposition of Samarium Thin Films
D. Yang, L. Xue (National Research Council Canada)

Samarium oxide thin film is attractive for applications in microelectronic and opto-electronic devices due to its high dielectric constant and low likelihood of interaction with silicon substrate during processing to form silicides. In this paper, we will present results on the characterization of samarium oxide thin films deposited by pulsed laser deposition (PLD) technique on silicon substrates at a temperature range of 25 - 680°C.

Samarium oxide films were grown on silicon wafers of 75-mm diameter using a KrF excimer laser at a wavelength of 248 nm and a repetition rate of 50 Hz. The laser beam was focused onto a 90-mm diameter Sm2O3 target to induce its ablation in 30 mTorr of O2 process gas. The uniform coverage up to 75 mm diameter was obtained by rastering the laser beam over the rotating target, while the substrate was rotated simultaneously. The crystallinity of films was investigated by X-ray diffraction (XRD). The morphology and particulate contamination of the film was evaluated using scanning electron microscopy (SEM). The thickness, the index of refraction, n, and extinction coefficient, k, of the samarium oxide films were measured by spectrophotometry in the wavelength region of 220-860 nm.

2:30 PM H2-2-4 Properties of Low Dielectric Constant Nanoporous Polymer Films and Dependence on Porosity
C.M. Flannery, S. Kim, D.C. Hurley (National Institute of Standards and Technology); M.R. Baklanov (XPEQT at IMEC, Belgium)

The demand for miniaturization in the microelectronics industry requires that the RC (resistance-capacitance) factor be lowered to reduce interconnection delay, crosstalk and power loss. The most promising way to achieve this is by introducing porosity into the dielectric film material. This is achieved by use of a sacrificial nanoparticle technique. Initially composed of a mixture of thermally stable oligomer and thermally unstable spherical organic polymer particles, the unstable particles diffuse out during heating, leaving well-defined voids of 3.5 nm diameter. The remaining organic matrix vitrifies and leaves a nanoporous structure with reduced dielectric constant. The amount of porosity introduced can be tuned by the amount of unstable organic particle introduced.

Introducing porosity has a very large effect on the critical properties of the material. The stiffness properties reduce drastically and the material may be too soft or brittle too be used in a commercial application. The dielectric constant relation to porosity is complex and depends on pore size, distribution and level of impurity. The variation of Poisson's ratio is not at all understood. In this work we show the techniques of surface acoustic wave spectroscopy, where dispersion of a laser-generated acoustic wave propagating along the surface of a sample allows one to determine the stiffness and density of the material, and Brillouin light scattering, where frequency shifts of photons colliding with ambient thermal phonons in the material provides data about stiffness, pore size and Poisson's ratio, may be successfully applied to these materials. We explore the complex relation between stiffness, dielectric constant and porosity and how they are related to pore size and distribution. This is demonstrated on several sets of nanoporous polymer films of varying porosity and pore dimension. Complementary measurements from nanoindentation and X-ray scattering are compared and evaluated.

2:50 PM H2-2-5 Extraction of Electrical Mechanisms of Low-dielectric Constant Material MSZ for Interconnect Applications
S.T Yan (National Chiao Tung University, Taiwan, ROC); T.C. Chang (National Sun Yat-Sen University, Taiwan, ROC); P.T. Liu (National Nano Device Laboratory, Taiwan, ROC); Z.W. Lin, S.M. Sze (National Chiao Tung University, Taiwan, ROC)
For the purpose of reducing RC time delay in the interconnections of integrated circuits, low dielectric constant (low-k) materials as inter-metal dielectric (IMD) have been extensively investigated. In this paper, physical and electrical characterization of new low-k dielectric Methyl-silsesquiazane (MSZ) is presented. Thermal stress and bias temperature stress (BTS) were utilized to evaluate the influence of Cu penetration on dielectric properties. In the investigation of thermal stress performed by furnace annealing, the leakage current of Al-gate MSZ capacitor is decreased with both elevated temperatures and stressing time due to the decrease of the interfacial states between the metal and dielectric. For Cu-electrode samples, the decreasing interface states cannot compete with the increasing defects resulted from Cu penetration. Therefore, the leakage current of Cu-gate MSZ is increased with elevated temperatures and stressing periods. Even so, the leakage behavior of Cu-gate samples is still so small that can meet the tolerance of interconnection operation. Based on BTS methods, it is concluded that MSZ is Cu resistant at high field and high temperature stressing and is a suitable candidate for IMD in multi-level interconnects. Furthermore, leakage conduction mechanism at high electric field is deduced from Schottky emission in conjunction with space-charge-limited current conduction (SCLC) through BTS methods.
3:10 PM H2-2-6 A Combinatorial Workflow for the Rapid Discovery and Optimization of Low Dielectric Constant Materials
K. Chondroudis, K. Cendak, E. Ramberg, M. Devenney (Symyx Technologies, Inc.); S. Weigel, J. Kirner, J. MacDougall, T. Deis (Air Products and Chemicals, Inc.)

Combinatorial synthesis and screening of extraordinarily large numbers of different organic compounds has been widely applied in the pharmaceutical industry for drug discovery. At Symyx, combinatorial high throughput synthesis and screening techniques have been implemented to create integrated workflows that enable scientists to discover and optimize materials across a broad range of applications at an accelerated rate compared to traditional techniques.

There is an urgent need in the semiconductor industry for the identification and development of next generation low dielectric constant (low-k) films and several groups are exploring the use of spin-on low-k solutions. Symyx has constructed and utilized a combinatorial workflow for the rapid discovery and optimization of spin-on, porous low-k films. In this talk we will discuss how combinatorial techniques were used to:

a) Design the desired parameter space (e.g. composition) of a multi-component solution system,

b) formulate the designed solutions in a microliter scale,

c) rapidly dispense and fabricate low-k film libraries from these solutions,

d) efficiently screen the films for optical properties, dielectric constant and mechanical properties and

e)capture the data and use the information to discover dielectric films with low dielectric constant and high modulus.

This workflow allowed us in approximately 8 months to study more than 12,000 compositions, identifying materials with superior properties. These new compositions were subsequently scaled-up (i.e. prepared in a conventional spin-coated format and scale) successfully confirming the properties as identified by the library data.

3:30 PM H2-2-7 CMP of Ultra Low-k Material Porous-polysilazane (PPSZ-M) for Interconnect Applications
T.C. Chang (National Sun Yat-Sen University, Taiwan, ROC); T.M. Tsai (National Chiao Tung University, Taiwan, ROC); P.T. Liu (National Nano Device Laboratory, Taiwan, ROC); C.W. Chen, S.T Yan, H.C. Tseng (National Chiao Tung University, Taiwan, ROC); H. Aoki (Clariant Corporation, Japan); T.Y. Tseng (National Chiao Tung University, Taiwan, ROC)
An ultra low-k (k≤2.2) material Porous-Polysilazane (PPSZ-M) CMP was investigated for its feasibility in the interconnect system. Surface planarization is a key technology during the manufacture of multilevel interconnects. The chemical mechanical polishing (CMP) process is satisfactory for the requirement of global topography planarization and etchback technology. Moreover, since it is difficult to determine the end point of Cu and Ta polishing during CMP processes, it must be evaluated whether the dielectric properties of films would be degraded during this process. There were three slurries employed to estimate the compatibility of PPSZ-M film during CMP process in this paper. First is conventional silica-based slurry which is commercially utilized to polish SiO2 in conventional metallization system. Other two types of aluminum oxide-based and colloidal silicate slurries are used to polishing Cu and Ta metal in interconnect system, respectively. It was found that surface planarity would not be degraded during CMP with above-mentioned slurries. In addition, the dielectric constant and leakage current density of post-CMP PPSZ-M films would not be deteriorated, indicating the ultra low-k PPSZ-M films are promising for use as an inter-metal dielectric in multilevel interconnects.
3:50 PM H2-2-8 Evaluation of Advanced Chemical Mechanical Planarization Techniques for Copper Damascene Interconnect
K.W. Chen (National Chiao-Tung University, Taiwan, ROC); Y.L. Wang (Taiwan Semiconductor Manufacturing Co., Ltd,, Taiwan, ROC); K.Y. Lo (National Chia Yi University, Taiwan, ROC); C.P. Liu (National Cheng-Kung University, Taiwan, ROC)
According to rapid development of CMP technology, the difference of polishing methods would be applied for copper damascene interconnect. Theses methods include conventional rotary, linear, oscillation platform. The advantages of these platforms would be highlighted in uniformity control, stability of removal rate, planarization efficiency, throughput promotion, lower cost of ownership, even dishing and erosion effect integrated with slurry. This paper presented our experience to compare the uniformity, removal rate, and planarization efficiency of Cu-CMP between various polishing platforms. In convection, the rotary or oscillation platform would be usually applied in oxide and tungsten CMP, due to the robust air-back carrier and rigid platen to polish the wafer, which performs the good reliability on wafer-to-wafer thickness and endpoint detection. On the other hand, the linear polisher is made of the air-bearing moving belt and self-rotated carrier, and would provide the wider uniformity and planarization control window than others. In addition, the simulation model would explain the difference from mechanic design and wafer moving paths between various polishing techniques. To compare these performances of uniformity and removal rate, the linear polisher would provide the better uniformity control, but rotary ones have the better wafer-to-wafer variation control. Hence, the trade-off advantage and application between various platforms would be compensated and integrated with slurry, conditioners, and coming thickness profile from copper plating. It can achieve the optimization of Cu-CMP process.
4:10 PM H2-2-9 Prevention of Damage of PR Removal by E-beam Direct Patterning on HSQ Films for Interconnect Applications
Z.W. Lin (National Chiao Tung University, Taiwan, ROC); T.C. Chang (National Sun Yat-Sen University, Taiwan, ROC); P.T. Liu, B.C. Chang (National Nano Device Laboratory, Taiwan, ROC); S.T Yan, C.C. Lo (National Chiao Tung University, Taiwan, ROC)
The demise of optical lithography was predicted to occur when IC feature size reached about 1 µm. So the electron beam lithographic process may be used for the layers with the smaller size. The films can be directly patterned using the lithographic process. Such technology does not need to use photoresist process. Therefore, it effectively avoids the damage from O2 plasma ashing. The low-k films will be degraded by the damage from O2 plasma during ashing process. The leakage current and dielectric constant will be degraded. In this study, we use e-beam to cure the HSQ films. The study is divided into two parts: (1) the sample was made by a metal-insulator-semiconductor (MIS) structure. Afterward, the leakage current and dielectric constant were characterized before and after dipping in developer solution. (2) After e-beam exposure, the line is patterned on HSQ films, followed by dipping in developer solution. SEM is used to show the cross-section profiles. It is found the films have good leakage characteristics and low dielectric constant using e-beam lithographic process. The linewidth can be achieved to 0.06 µm or smaller. So the e-beam lithographic process is potential technique for next generation.
4:30 PM H2-2-10 A Study of Silicon Carbides Doped with Oxygen and Nitrogen
Y.L. Cheng (National Chiao-Tung University, Taiwan, ROC); Y.L. Wang (Taiwan Semiconductor Manufacturing Co., Ltd,, Taiwan, ROC); K.Y. Lo (National Chia Yi University, Taiwan, ROC); C.P. Liu (National Cheng-Kung University, Taiwan, ROC)
Silicon carbide (SiC) with lower dielectric constant (k=5.0) is a good candidate of dielectric barrier/etch stop and cap layer for Cu/low-k damascene. In this study, we have investigated the properties of SiC doped with different amounts of oxygen and nitrogen. Various SiC films were deposited with trimethylsilane (3MS) as a precursor mixed with carbon dioxide (CO2), ammonia (NH3) and helium (He) by plasma enhanced chemical vapor deposition (PECVD). Film properties in SiC film can be modify by incorporating different nitrogen and oxygen. The chemical compositions of SiC films were characterized by FTIR. The results show that higher ratio of CO2 to NH3 or increased O:N ratio leads to higher deposition rate and lower R.I. The dielectric constant is no significant change, and the leakage and breakdown are improved with more oxygen addition. Although improved breakdown field and lower dielectric are desired, from pressure cook test, the films are however found permeable to moisture. The degradation of dielectric constant in subsequent process steps, such as etch and CMP, was found due to more Si-H bonding appearing in SiC with higher O/N ratio.In this paper, the trade-off of chemical, physical, mechanical, and electrical properties of SiC by varying deposition processes, mainly for O/N optimization, will be discussed.
4:50 PM H2-2-11 Copper Surface Protection with a Completely Enclosed Copper Structure for a Damascene Process
T.C. Wang, T.E. Hsieh (National Chiao-Tung University, Taiwan, ROC); Y.L. Wang (National Chiao-Tung Univ. and Taiwan Semiconductor Manufac. Co., Ltd, Taiwan, ROC); C.W. Liu, Y.K. Lin (Taiwan Semiconductor Manufacturing Co., Ltd., Taiwan, ROC); K.W. Chen (National Chiao-Tung Univ. and Taiwan Semiconductor Manufac. Co., Ltd, Taiwan, ROC)
As integrated circuit manufacture moving to copper interconnection for the most advanced products, protection of copper (Cu) surfaces becomes a major challenge for the back-end-of-line manufacturing process. The damages on Cu, such as Cu corrosion and oxidation, are often observed on wafers when exposing bare Cu surface in the presence of moisture and/or acidic gases. The corrosion destroys Cu surface. Furthemore, the Cu oxide results in poor adhesion both at Cu/barrier layer and Cu/stop layer interfaces. The Cu oxide also enhances the Cu hillock during thermal process. In this work, a novel Cu dual damascene structure which completely encloses the Cu surface with a TaN layer is presented. This capping layer avoids the Cu corrosion and oxidation due to its ability to keep moisture and acid off and away from the Cu surface.
Time Period ThA Sessions | Abstract Timeline | Topic H Sessions | Time Periods | Topics | ICMCTF2003 Schedule