AVS 66 Session EM+AP+MS+NS+TF-ThM: Advanced Processes for Interconnects and Devices

During our research to define a contact which can be serve as thin hard mask in III/V semiconductor processing, we focused on the Bell contact which consists of Ti/Pt(Mo)/Au and chlorine-based plasmas generated by electron cyclotron resonance. For platinum, we identified PF₃ as main component which acts comparable to CO [1]. This fact triggered our search for suited etchants for gold and copper. For Au, the best ambient is a mixture of CH₄, Cl₂, and O₂ which is stabilized by Ar [2]. This mixture generates residual-free etching of metal films which are clearly free of "fencing" and "hear's ears."

The etching process has been established up to thicknesses of half a micron which is the typical thickness of metal films on the p-side of laser devices. With the aid of optical emission spectroscopy, the generation of CO could be proven [3]. This reagent seems to be the main component for real etching without residual fencing.

[1] G. Franz, R. Kachel, and St. Sotier, Mat. Sci. Semicond. Proc. 5, 45 (2002)

[2] G. Franz, R. Meyer, and M.-C. Amann, Plasma Sci. Technol. 19, 125503 (2017)

[3] G. Franz, W. Oberhausen, R. Meyer, and M.-C. Amann, AIP Advances 8, 075026 (2018)

As conventional 2-D transistor scaling approaches its limits, 3-D architectures promise to increase the number of devices and reduce interconnect congestion. A process able to monolithically integrate single-crystalline group IV materials into the back-end-of-line (BEOL) may enable such designs. Here, we demonstrate the graphene-template assisted selective epitaxy (G-TASE) of single-crystal Ge on amorphous substrates at temperatures as low as 250 ^°C. This work represents a significant step forward for TASE methods, which have been largely limited to III-V and II-VI materials, bulk crystal templates, as well as higher temperatures. We specifically grow Ge nanostructures on graphene-on-oxide at the bottom of nanometer-scale oxide trenches by leveraging differences in group IV atom sticking probability between graphene and oxide surfaces. Raman mapping confirms the single crystallinity of as-grown Ge crystals. Time-dependent studies show a linear increase in Ge crystal height even after emerging from the oxide trench, indicating Ge atoms preferentially adsorb to the top facet under our growth conditions. Our studies also reveal that G-TASE is sensitive to the plasma process used to expose graphene in the oxide trenches. This work extends TASE to a new, technologically-relevant materials system and provides fundamental insight into the underlying physicochemistry.

KEY WORDS: silicon, germanium, epitaxy, graphene, selective deposition

Moore’s law drives continued device miniaturization in nano-electronics circuits. As critical dimensions are approaching the single nanometer length scale, the semiconductor industry is seeking novel technologies for precisely tailoring materials and structures at the atomic scale. While vapor-phase, plasma-assisted techniques of atomic layer deposition (ALD) and etching (ALE) are capable of providing nano-scale control over metal deposition and etching, these processes may not provide the requisite atomic-scale precision. Additionally, ALD precursors are unstable and often expensive. Thus, alternative solution-phase electrochemical processes are being developed in our laboratory. In our electrochemical ALD (e-ALD) approach, a sacrificial monolayer of zinc is first deposited on the noble substrate via underpotential deposition (UPD). The zinc adlayer then undergoes spontaneous surface-limited redox replacement (SLRR) by the desired metal such as Cu or Co. Sequential UPD and SLRR steps enable fabrication of multi-layered deposits in a layer-by-layer fashion. An analogous approach for electrochemical ALE (e-ALE) is also being developed. In electrochemical ALE of Cu, surface-limited sulfidization of Cu forms a cuprous sulfide (Cu₂S) monolayer. The sulfidized Cu monolayer is then selectively removed through spontaneous complexation of the Cu⁺¹ in a chloride-containing etchant medium. The sequence can be repeated to etch bulk metal films one atomic layer at a time. This talk will highlight numerous advantages and fundamental characteristics of e-ALD and e-ALE processes and describe opportunities for integrating them in wafer-scale metallization applications.

In order to improve device performance of interconnects, the microelectronics industry utilizes low- κ dielectric technology in place of traditional SiO₂. Integration of these materials into circuits has, however, been challenging due to poor mechanical stability as a result of the increased dielectric porosity. Large thermal stresses may also build up during successive thermal cycling due to differences in the thermal expansion of component materials. These adverse features become more prominent as smaller dimensions are sought for improvement in device performance. While titanium nitride (TiN) is currently being widely used as a hard mask to pattern low- κ materials such as SiOC:H into desired architectures with < 100 nm length scales, the high stress and stiffness of the TiN over-layer can influence the delicate underlying patterns and affect device performance.

In this study we utilize Brillouin light scattering (BLS) to probe the elastic properties of TiN/SiOC:H structures grown on Si that have been patterned into a series of parallel wires of rectangular cross-sections with sub 200 nm pitch and depths. In studying the influence of the hard mask on the mechanical properties of SiOC:H, BLS offers a non-invasive approach to detect thermally activated acoustic excitations and to measure their mode dispersions for incident light with wave-vector components parallel or perpendicular to the TiN wires. The widely-used technique of nanoindentation (NI) to measure mechanical properties has been shown, for ultra-thin soft films, to interact with the underlying substrate, thus skewing the results. On the other hand, the inelastic light scattering approach probes ambient modes allowing for the individual acoustic behavior of the film to be distinguished from the substrate.

In this research, we report the wafer-scale fabrication of carbon nanotube or graphene-based electronic device such as field-effect transistors (FETs). Carbon nanotube-based devices were fabricated with the alternating electric field-directed dielectrophoresis (DEP) method, and the graphene-based devices were fabricated with the carbon films grown with plasma-enhanced atomic layer deposition (PEALD) or e-beam evaporation. Semiconducting carbon nanotubes were dispersed ultrasonically in solutions, and were deposited and aligned onto a pair of gold electrodes in the fabrication of carbon nanotube-based electronic devices using the dielectrophoresis method. The DEP-aligned tubes were further fabricated into carbon nanotube field-transistors (CNTFETs) and CNTFET-based electronic devices such as CNT-based inverters and ring oscillators using the microfabrication techniques. The fabricated devices were imaged using the scanning electron microscope (SEM) and high-resolution transmission electron microscope (HRTEM), and the electrical properties were measured from the fabricated devices using the semiconductor analyzer. The semiconducting CNTs achieved higher yield in the device fabrication, and the fabricated devices demonstrated excellent electrical properties.