AVS2001 Session PS+MS-ThM: Conductor Etch and Damage

Thursday, November 1, 2001 8:20 AM in Room 104

Thursday Morning

Start	Invited?	Item
8:20 AM		PS+MS-ThM-1 An Advanced 300 mm Etcher with Tunable Plasma Source for the Etching of <0.15mm Poly-Silicon Gates J. Holland, M. Jain, M. Shen, N. Gani, A.M. Paterson, V. Todorov, M.S. Barnes, K. Fairbairn (Applied Materials, Inc.) The current requirements for etch performance for 300mm poly-silicon gate can only be met by providing a wide enough process window that is capable of achieving uniform etching for the variety of steps needed to complete this etch. The final dimensions of the polysilicon gate are functions of the many different etch steps, the ARC/DARC open, the main-etch , soft landing step and over-etch steps. In order to achieve < 10 nm CD range for <0.15 um polysilicon features, all of these steps need to be very uniform and the CD loss (or gain) needs to be very controllable. In this next generation 300 mm etcher, a tunable inductively coupled plasma source combined with advanced gas injection technology allows etch uniformity to be optimized for all of these different steps. Results of tuning for etch uniformity will be shown. CD control of <5 nm with a total range of 10 nm is achieved. The tunable source is also combined with a precise wafer temperature control using a dual-zone electrostatic chuck to ensure CD uniformity can be achieved across the entire diameter of the 300mm wafer. The wide process window of this etcher should be capable of addressing both current and evolving applications which require etching of multiple films with multiple etch steps involving varied process conditions.
8:40 AM		PS+MS-ThM-2 Plasma-Based Copper Etch Process - Additive Gas Effects S. Lee, Y. Kuo (Texas A&M University) Copper is an ideal multilevel interconnection material for VLSIC and many other microelectronic devices. However, it is difficult to etch copper into fine lines by the conventional plasma etching method under a mild process condition such as at room temperature or without the inclusion of an extra energy source, e.g., UV, IR, or a high-density plasma source. Recently, authors reported a new plasma-based copper etching method that showed a high etch rate at room temperature using a parallel-plate electrode design.^1,2 The success of this method relies on a novel plasma-copper reaction. Instead of removing copper compounds during the plasma processing, copper was converted into a solution soluble compound accumulated on the surface. This reaction product was subsequently removed with a HCl solution. The resulting copper pattern has a vertical profile. In this paper, we are going to discuss the additive gas (Ar, N₂, CF₄, and O₂) effects on the Cl₂ plasma-based copper reaction process. In addition to the reaction rate, the product's morphology, structure, and the undercut of the photoresist pattern have been studied. The added gas can enhance or hinder the reaction rate and the progress in the radial direction through various mechanisms. Experimental results are interpreted by the plasma phase chemistry, ion bombardment phenomena, and the original copper structure. The composition and chemical states of the reaction product are characterized by EDS and XPS. The film's morphology and structure are examined by AFM, SEM, and XRD. This study enhances our understanding of the unique plasma-based copper etching process that is critical to many microelectronic and optoelectronic applications. Authors would like to acknowledge staffs in the CIMS of Texas A&M University for AFM and XPS analyses. ¹ Y. Kuo and S. Lee, Appl. Phys. Lett. 78, 1002, (2001) ² Y. Kuo and S. Lee, Jpn. J. Appl. Phys. 39, L188, (2000).
9:00 AM	Invited	PS+MS-ThM-3 Silicon Gate Etching: Potential Strategies for Future CMOS Devices G. Cunge, L. Vallier, O. Joubert, J. Foucher, X. Detter (CNRS/LTM, France) In less than ten years CMOS devices will operate in the sub-50 nm gate length regime. The fabrication of the gate will be the key issue of the device fabrication process since the variation in gate dimension must not exceed the nominal CD targeted by few nm. In this work, some of the most promising gate strategies are investigated 1) resist mask on SiON antireflective layers versus hard mask approaches 2) standard HBr/Cl₂/O₂ chemistries versus CF₄ (or NF₃) added chemistries. The origin of CD deviation are investigated for each single step of the different strategies: correlations between chemistry and plasma operating conditions analysed by mass spectrometry, passivation layer formation on the feature sidewalls analysed by XPS and CD deviation will be established. Our preliminary experiments show that the passivation layers formed on the mask sidewalls induce very severe CD gain during standard gate etch steps. The objective is first to minimize the CD deviation induced by each individual step of the process (by decreasing the passivation layer thickness). Ultimately, the process has to be tuned so that the CD loss or gain of each individual step compensate each other to maintain the CD in the targeted window. In final, by comparing the impact of mask materials as well as the impact of chemistries (standard or clean) on CD control, we may give some interesting conclusions on the most promising strategy. In parallel to this study, we evaluate the current strategies used to obtain gates smaller than the dimension printed by the lithography (resist trimming or "notched gate approach") and try to draw some clear conclusions on the best approach for manufacturing.
9:40 AM		PS+MS-ThM-5 Sidewall Passivation Mechanism of CF₄ Added Polysilicon Gate Etch Process T. Lill, F. Ameri, S. Deshmukh, D. Podlesnik (Applied Materials); L. Vallier, O. Joubert (CNRS/LTM, France) For the traditional HBr/Cl₂/O₂ gate etch process, anisotropy is achieved by forming silicon, oxygen, and halogen containing compounds on the sidewall of the etching structures. These compounds inhibit the isotropic etch and are removed by from the etch front via ion sputtering and ion assisted desorption. The introduction of fluorine via CF₄ to a typical HBr/Cl₂/O₂ polysilicon etch process suppresses the formation of SiOxBry or SiOxCly via formation of volatile SiF₄. Speculations that carbon based polymers play an important role in the sidewall mechanism for the CF₄ polysilicon gate etch chemistry have recently been confirmed by in-situ XPS studies in the Silicon DPS chamber at CNRS/LETI in Grenoble. In this paper we present more detailed studies of the sidewall composition for different CF₄ and O₂ flows. The results suggest the coexistence of silicon oxyhalogenides and carbon polymers on the sidewall for theHBr/Cl₂/CF₄/O₂ gas mixture. The carbon content in the sidewall passivation layer increases strongly when the oxygen flow is reduced. The XPS results will be correlated with findings on chamber wall condition (oxide or carbon mode), change of the critical dimension for dense and isolated lines during gate etching (critical dimension microloading), and etch rate differences between doped and undoped polysilicon. We will present experimental line width data that corroborate the idea of change in sidewall passivation from compounds that are formed on the etching surface (silicon oxyhalogenides) to compounds formed in the gas phase (carbon polymers) when CF₄ is added to the plasma. Typically, profile and critical dimension microloading are significantly reduced for the CF₄ added chemistry as a result of the change in the sidewall passivation mechanism. The superior etch performance and the increased productivity due to clean chamber walls explain the rapid acceptance of this polysilicon gate etch chemistry in high volume VLSI production.
10:00 AM		PS+MS-ThM-6 Manufacturing Viability of the "Notched Gate" Process for sub 0.1µm Technologies J. Foucher, L. Vallier, G. Cunge, O. Joubert (CNRS/LTM, France); T. Lill (Applied Materials) The development of new integrated circuit generations, at a unique rate in the semiconductor history, imposes the development of new technologies. Recently, Integrated Circuit manufacturers have evaluated new strategies to make gate transistors smaller than the resolution allowed by the lithographic tool available for manufacturing. One of them is to decrease the resist feature dimension before gate etching (resist trimming), the other approach is to design a "notched gate" etch process with a controlled etch rate of silicon in the lateral direction (the bottom of the gate is smaller than its top). We first describe in details the main differences between a notched gate process and a standard gate etch process and introduce the notion of passivation layer engineering. We demonstrate that when the process is accurately tuned, gate dimension of 10 nm can be obtained on a 200 mm diameter wafer. We mainly concentrate on several aspects of the process which determine its industrial viability: - What are the plasma operating conditions and chemistry required to stabilize a "notched gate" process or in other words what are the impact of the wall conditions on notch reproducibility ? - Can we solve the CD control issues of the notched gate process ? We will present experimental data demonstrating clearly that the notch depth rate is strongly dependent on the gate environment. In other words, the lateral etch rate which controls the notch depth is aspect ratio dependent and impacted by the plasma non-uniformity. In conclusion, we clearly demonstrate the strong limitations of the notched gate process for manufacturing.
10:20 AM		PS+MS-ThM-7 Properties of Pulsed ICPs with rf Substrate Biases¹ P. Subramonium, M.J. Kushner (University of Illinois) Pulsed inductively coupled plasmas (P-ICPs) are of interest for controlling reactive fluxes to the substrate in microelectronics fabrication. In particular, negative ion fluxes to the wafer can be obtained in electronegative pulsed plasmas. In order to achieve anisotropy of the fluxes, rf substrate biases must also be used with P-ICPs. This is problematic since the increase in plasma potential obtained with an rf bias tends to trap negative ions. A moderately parallel implementation of the 2-dimensional Hybrid Plasma Equipment Model (HPEM) was used to investigate P-ICPs in electronegative gas mixtures having continuous and pulsed rf substrate biases. Electron properties are obtained using a Monte Carlo Simulation. In Cl₂ at 10 mTorr (PRF=10 kHz, duty cycle 50%), the electron temperature, after falling in the first part of the afterglow, increases in the late afterglow signifying a transition to a capacitive mode. The onset of the increase in T_e comes earlier with increasing rf bias voltage. The increase can be attributed to progressively larger rates of sheath heating resulting from the decreasing electron density, increasing sheath width and increasing sheath speed. Coincident with the increase in T_e comes an increase in sheath potential which prevents negative ions from escaping from the plasma. ¹ ¹Work supported by NSF, SRC and Applied Materials.
10:40 AM		PS+MS-ThM-8 Magnetic Field Effects and Electron Shading Damage W.W. Dostalik (Texas Instruments, Inc.) The use of magnetically enhanced plasma etch systems (MERIE) is widespread in semiconductor manufacturing. A primary concern with such systems is the risk of plasma process induced damage. In this paper, we discuss several of the candidate mechanisms in which magnetic fields may affect plasma damage associated with the electron shading effect (ESE). In particular, we consider for the case of a permanent magnet MERIE reactor the effects of guiding center drifts (e.g., gradient drift and curvature drift) on charged particle fluxes, of magnetic field effects on individual trajectories, and of non-uniformity in a typical magnetic field map. These effects are calculated in a two-step fashion. In the first step, an experimentally measured magnetic field map of a commercial plasma reactor is input into a computer program that calculates the various drift velocities and non-uniformity for typical plasma parameters. In the second step, the results of these calculations are used to affect incoming charged particle fluxes in local scale Monte Carlo simulations including the magnetic field and local topography. Charge accumulation and the resulting Fowler-Nordheim injection current are accounted for in the Monte Carlo simulations.
11:00 AM		PS+MS-ThM-9 Effects of H₂, D₂, N₂ and Ar Plasma on III-V Compound Semiconductor Devices B. Luo (University of Florida); K. Ip (Agere Systems); F. Ren, K.P. Lee, S.J. Pearton, C.R. Abernathy (University of Florida); R.J. Shul (Sandia National Laboratories); S.N.G. Chu (Agere Systems); C.W. Tu (University of California, San Diego); C.S. Wu (Win Semiconductor); K.D. Mackenzie (Unaxis USA Inc.); C.H. Hsu (Feng Chia University, Taiwan) The effects of H₂, D₂, N₂ and Ar plasma exposures on the dc and rf characteristics of pseudomorphic AlGaAs/InGaAs high electron mobility transistors (HEMTs), GaAs metal semiconductor field effect transistors (MESFETs), and AlGaAs/GaAs heterojunction bipolar transistors (HBTs) were investigated. The experiments were conducted in a Plasma Therm 790 inductively coupled plasma (ICP) system. The influences of rf chuck power(10-100W), ICP source power(100-800W), chamber pressure(2-10mtorr) and durations(10-240sec) on device performance were studied. To analyze the rf results, a device equivalent circuit model was proposed to realize damage effects on the transistor small-signal elements. Several plasma damage mechanisms were identified for the degradations of device dc and rf characteristics, including creation of surface and bulk deep level recombination centers, preferential loss of As atom from the surface due to energetic ion bombardment and passivation of Si donors by formation of Si-H and Si-D neutral complexes. Auger and atomic force microscopy (AFM) were also used to characterize the atomic ratio and roughness of plasma damaged surface, respectively.
11:40 AM		PS+MS-ThM-11 Plasma Induced Physical Damage and Contamination on the SrBi₂Ta₂O₉ Thin Film after Etching in Cl₂/CF₄/Ar Plasma D.P. Kim, C.I. Kim (Chung-Ang University, Korea); W.J. Lee, B.G. Yu (ETRI, Korea) SrBi₂Ta₂O₉ (SBT) have been developed as dielectric materials of capacitor. To fabricate high density FRAM, plasma etching is indispensable process for the anisotropic pattern definition because it has good selectivity and excellent process control. However, the detrimental impact of plasma etching process on device characteristics has been existed. As feature size decreases, the plasma induced damages can decrease the performance of device. The plasma induced damages can be broadly classified as residue contamination, plasma-caused species permeation, bonding disruption and current flow damage. Etching mechanism and damages on SBT thin film during etching process have less reported in the literature. SBT thin films were etched in Cl₂/CF₄/Ar plasmas with measuring etch rates at different etching parameters such as gas mixing ratio, rf power, dc bias voltage, and chamber pressure. The maximum etch rate was 1060 Å/min in Cl₂(10)/CF₄(20)/Ar(80). The small addition of Cl₂ into CF₄(20)/Ar(80) plasma will decrease the fluorine radicals and the increase Cl radical. The etch profile of SBT thin films in Cl₂/ CF₄/Ar plasma is over 80°. The chemical reactions on the etched surface were investigated with x-ray photoelectron spectroscopy (XPS). Atomic force microscopy (AFM) was used to investigate the surface morphology of SBT thin films exposed in plasma. High-resolution transmission electron microscopy (TEM), secondary ion mass spectrometry (SIMS) and x-ray diffraction (XRD) were evaluated in order to investigate physical damages. Electrical properties were characterized by measuring leakage current and hysteresys loop of Pt/SBT/Pt capacitor. From the results, damages in SBT etching was occurred in the near surface and Ar ion bombardment and nonvolatile etching by products caused to change of crystallinity and surface morphology.