High on-resistance due to low channel mobility and threshold voltage instability due to charge trapping are major concerns of SiC-based power MOSFET, and both issues are deeply correlated with poor SiO₂/SiC interface property grown by thermal oxidation. One of the main causes of this severe interface degradation is residual carbon impurity remained near SiO₂/SiC interface. Although the most common technique to improve SiO₂/SiC interface quality is N incorporation into SiO₂/SiC interface by post-oxidation annealing in NO (NO-POA), the effect on mobility improvement is limited [1] and enhanced hole trapping is pointed out [2]. In this talk, we review the scheme of thermal oxidation and control of N atom profile to improve performance and reliability of SiC MOSFETs based on our recent results.

We demonstrated ultrahigh-temperature oxidation at low oxygen partial pressure to enhance C ejection from SiO₂/SiC interface during thermal oxidation [3]. Passive/active oxidation boundary for 4H-SiC(0001) surface was found to be at around 1600°C under 0.3% O₂/Ar ambient. In SiC MOS capacitors, nearly ideal C-V curve can be obtained by ultrahigh-temperature oxidation, while large hysteresis and positive flatband voltage shift were observed for conventional oxidation. The field-effect mobility of nMOSFET increased from 3 to about 10 cm²/Vs by performing ultrahigh-temperature oxidation. The reduction in C-related defects was confirmed by electron-spin-resonance (ESR) spectroscopy [4]. We also found that SiC can be oxidized to form SiO₂ under CO₂ ambient at ultrahigh temperatures [5]. Furthermore, a combination of NO-POA and subsequent CO₂ annealing at moderate temperature is effective in obtaining high-channel mobility and stable threshold voltage thanks to the selective removal of N atoms on SiO₂ side at SiO₂/SiC interface and compensation of oxygen vacancies [6].

1. T. Hatakeyama et al., Appl. Phys. Express 10, 046601 (2017).
2. J. Rozen et al., J. Appl. Phys. 103, 124513 (2008).
3. T. Hosoi et al., Appl. Phys. Express 11, 091301 (2018).
4. T. Umeda et al., J. Appl. Phys. 127, 145301 (2020).
5. T. Hosoi et al., Appl. Phys. Express 14, 101001 (2021).
6. T. Hosoi et al., Appl. Phys. Express 15, 061003 (2022).

Remote epitaxy (RE) is a promising new technique for epitaxial film removal and substrate reuse that utilizes monolayer graphene as a release layer [1]. Graphene grown directly on SiC(0001) substrates through Si sublimation or through propane chemical vapor deposition (CVD) is an ideal platform for remote epitaxy of wide bandgap (WBG) semiconductors as there is no need for a graphene transfer step, reducing the risk of introducing contamination or defects that can complicate the study of the remote epitaxy process. In addition, this materials system is compatible with commercially-viable WBG semiconductor growth and processing. However, SiC CVD growth is typically conducted using high-temperature hydrogen-based chemistries that could damage or remove graphene. This study investigates the effect of alternate CVD growth conditions on SiC/graphene/SiC(0001) remote epitaxy and optimizes CVD parameters to produce high-quality SiC epilayers while reducing damage to the graphene barrier. In addition, since the effect of epitaxial graphene features such as SiC macrostep morphology and associated layer inhomogeneity on the RE process is currently unknown, graphene preparation and associated morphology are varied to explore its effect on SiC epilayer formation.

Semi-insulating nominally on-axis 6H-SiC(0001) and n-type 4° off-axis 4H-SiC(0001) substrates were used to produce different SiC surface morphologies and graphene layer numbers. Ar:H₂ process gas flow ratio, growth precursor C/Si ratio, and growth temperature were optimized during hot-wall CVD RE to promote smooth film morphology. Nomarski optical microscopy, scanning electron microscopy, and atomic force microscopy found CVD deposition at 1620°C with Ar/H₂ ratios <20/5 slm, and C/Si ratios <1.55 to have the smoothest surface morphology and fewest polytype inclusions. Substrates with offcuts <0.1° from SiC(0001) exhibited lower epilayer macrostep density, but showed evidence of polytype impurities and 3D growth at C/Si ratios > 1.0. Point defect density in RE SiC epilayers using a graphene interface was shown to be lower than SiC homoepitaxy using similar conditions without graphene. Cross-sectional transmission electron microscopy was utilized to assess the growth interface and graphene layer integrity after CVD growth. Through this study, optimal RE growth processes are suggested for a balance of graphene survivability and SiC film morphology.

[1] Kim, Y., Cruz, S., Lee, K. et al. Nature 544, 340–343 (2017).

Power electronics materials are poised to play a critical role in fulfilling next generation energy needs, with up to 90% of future energy demand predicted to flow through power electronics at some point.[1] Among a number of candidate materials, AlxGa1-xN is the strongest, having bipolar dopability, thermal and chemical stability, an ultra-wide bandgap, and demonstrated experimental feasibility. However, AlGaN growth is limited by a lack of lattice-matched substrates, ultimately stunting material quality at higher thicknesses needed for power electronics applications. Further, high power applications increasingly call for fully vertical device structures, necessitating a conductive substrate. [1] Recently our group identified the (111) plane of TaC as a conductive surface lattice-matched to Al_0.55Ga_0.45N, taking inspiration from prior work of AlN and GaN binaries on carbide and boride substrates. [2,3,4]

In this talk we demonstrate the growth of (111)-oriented TaC by RF sputtering. We investigate the interface of TaC with sapphire and SiC substrates and identify means to suppress competing Ta₂C nucleation in order to stabilize (111)-oriented TaC. Potential stacking sequences are identified with respect to crystal structure and observed twinning in the TaC films. We next assess structural changes and film recrystallization that results from face-to-face annealing of TaC thin films at high temperatures above 1500 ºC. Changes to grain structure and domain size are assessed by x-ray diffraction and surface morphology is explored using atomic force microscopy. Fig 1 shows significant improvements to in- and out-of-plane strain following annealing along with the formation of terraced step edges at the film surface. Strain as a function of material composition and thickness is considered, as this may play a major role in future nucleation of AlGaN layers.

References

[1] R. J. Kaplar et al 2017, ECS J. Solid State Sci. Technol. 6 Q3061

[2] D. M. Roberts et al 2022, https://arxiv.org/abs/2208.11769

[3] T. Aizawa et al 2008, J Crys Growth 310, 1 22

[4] R. Liu et al 2002, Appl. Phys. Lett. 81, 3182-3184

The lack of lattice matched substrates for AlGaN is the primary limitation to achieving high-performance power electronics, high-frequency electronics, and deep UV (DUV) LEDs. This substrate limitation affects both material quality, through the formation of misfit-induced threading dislocations and strain-induced phase separation, and limitations to device geometry due to resistive or insulating electrical behavior. Dislocations and phase separation prevent AlGaN from reaching its full materials potential, and in the case of semiconducting substrates the primary loss mechanism in a vertically conductive device is resistive loss in the substrate itself. Thus, AlGaN alloys coulddrive disruptive technology iflong-standing substrate issues can be solved [1]. For Al_xGa_1-xN there are competing effects of increasing alloy scattering, increased bandgap with increasing Al fraction, and decreasing dopant activation such that ideal compositions for power devices fall in the range 0.3 < x < 0.85 [2]. For these compositions pseudomorphic growth on GaN and AlN is very difficult or impossible.

Recently we have reported the design of virtual substrates for Al_xGa_1-xNepitaxy consisting of (111) TaC_x grown on sapphire substrates via RF sputtering [3]. The crystallinity is subsequently improved by face-to-face annealing. These substrates offer several opportunities to improve power electronic devices through lattice and thermal conductivity matching, high electrical conductivity, high stability, and epitaxial liftoff.

There has been increased interest in ScAlN-barrier high electron mobility transistors (HEMTs) as ScAlN has larger spontaneous and piezoelectric polarization fields than those in GaN and AlN, which can lead to larger two dimensional electron gas (2DEG) densities. Also, ScAlN with 18% Sc content is nearly latticed matched with GaN and has bandgap of 5.65 eV. Thus, ScAlN can provide a strain-free barrier for GaN HEMT structures with high carrier concentration. Recently, we have demonstrated ScAlN-barrier GaN HEMT structures with electron mobility of 910 cm²/V-s and 2DEG density >3x10¹³ cm^-2 [1]. However, these ScAlN/GaN HEMT devices still suffer from high leakage current [2]. Integrating gate dielectrics into these novel ScAlN-barrier HEMTs is necessary to decrease the leakage current, maintain high electric field breakdown and mitigate dc-RF dispersion in order to realize the full potential of these devices.

In this talk we report growth optimization and electrical properties of atomic layer deposition (ALD) grown TiO₂ gate dielectric on ScAlN-barrier HEMTs using Ultratech Fiji Gen2 ALD reactor. ALD process windows were initially monitored and optimized on Si substrates using in-situ ellipsometry. Films were deposited using tetrakis(dimethylamino)titanium (TDMAT) and an Ar/O₂ plasma at 300W. The TDMAT precursor temperature was maintained at 75 ^oC, while the pulse duration was varied from 0.25 to 0.35 sec. The plasma gas chemistry was also optimized. Optimal deposition parameters were used as initial condition to further optimize ALD conditions on ScAlN surface. On ScAlN barrier HEMT structures, deposition temperature was varied from 150 to 350 ^oC.

Atomic force microscopy was measured before and after ALD deposition showing minimal change in roughness as a result of the TiO₂ deposition.Contactless resistivity measurements performed before and after ALD and were also consistent, indicating that no plasma induced damage was occurring during ALD gate deposition. Vertical current-voltage and capacitance-voltage measurements were made on a Schottky-contacted HEMT structure and compared to devices with TiO₂ gate dielectrics deposited at different temperatures to discern the full electrical impact. As an example, an extracted dielectric constant of TiO₂ layer deposited at 200°C with O₂ flow of 20 sccm was 50 with no significant change in 2DEG density (changed from 2.7x10¹³ cm^-2 to 2.6x10¹³ cm^-2after TiO₂ layer). Finally, we will present the band alignment of an optimum ALD TiO₂ on ScAlN structure using x-ray photoelectron spectroscopy.

References:

1. Hardy et al., Appl. Phys. Lett.110, 162104 (2017).
2. Green et al., IEEE Electron Device Letters40, 1056 (2019).

Interest in vanadium dioxide (VO₂) comes from its ability to undergo a metal-to-insulator transition (MIT) from monoclinic, semiconducting M1 phase to the metallic, rutile R phase. This transition occurs at a temperature of 340 K [2] and is generally characterized by a rapid change in electrical conductivity. This makes VO₂ attractive for many electronic and optical switching applications [1,3-4].Research on VO₂ thin film deposition has run the gamut in terms of the substrates and deposition methods used, but the use of bulk yttria-stabilized zirconia (YSZ) substrates and RF sputtering in combination or CMOS compatible fabrication has not been emphasized.

In this talk, we demonstrate that the growth of VO₂ (M1) thin films and the magnitude of the MIT (on/off ratio) are strongly impacted by choice of substrate and deposition method, and these choices are not trivial. This is achieved by comparing reactive RF sputtering deposition and oxidation of a polycrystalline vanadium metal film sputtered on (100)- and (111)-oriented YSZ substrates. The dioxide stoichiometry of these films is confirmed by x-ray photoelectron spectroscopy (XPS) and Raman spectroscopy. X-ray diffraction (XRD) reveals that direct reactive sputtering on both substrate orientations yields VO₂ (B), a metastable phase epitaxially stabilized by lattice matching. The metal sputtering and subsequent oxidation process (Fig. 1a) on (100)-oriented YSZ results in (010)-oriented VO₂ (M1) exhibiting an MIT on the order of 10³confirmed by temperature dependent conductance measurements (Fig. 1b) in CMOS compatible devices. With the same metal sputtering and subsequent oxidation process on (111)-oriented YSZ, we achieve slightly overoxidized films with similar magnitude of MIT.

[1] Zhou, Y; Ramanathan, S. Proceedings of the IEEE, 103(8), 1289 (2015)

[2] Morin, F. J. Phys. Rev. Lett., 3(1), 34 (1959)

[3] McInerney, J. G.Proceedings of SPIE, Cambridge, MA, United States, January 1, 1987; Vol. 836, 234

[4] Lysenko, S.; Rua, A. J.; et al.Appl. Surf. Sci., 252(15), 5512 (2006)