AVS 72 Session PS1-WeM: Plasmas for 3D Integration

Three-dimensional (3D) interconnect technology based on die vertical stacking has been attracting increasing attention recently as a key approach to extend system-level performance beyond conventional scaling limits [1]. Through-silicon vias (TSVs), through-dielectric vias (TDVs), and nano-TSVs (nTSVs) used in backside power delivery networks enable high-density vertical electrical signal or power transport in heterogeneous 3D integration.

3D interconnect performance depends not only on interconnect structures but also on upstream processes such as plasma dicing, which ensure die integrity and bonding yield. Reducing wafer thickness and downsizing dies have revealed the limitations of conventional mechanical and laser dicing methods, while plasma dicing offers precise and clean die singulation [2].

This work focuses on the challenges faced by the plasma etching community in delivering high-aspect-ratio processes with tight control of anisotropy at both the macroscale (TSV, TDV, and plasma dicing) and the nanoscale (nTSVs). In addition to profile performance, other important parameters such as high selectivity to photoresist (PR) and hard mask (HM), as well as endpoint detection in very small open areas with dense layouts, are addressed.

TSVs and nTSVs are both affected by etch-rate suppression and profile distortion due to aspect-ratio-dependent etching [3, 4]. For nTSVs, these challenges are exacerbated by the need for nanoscale precision, especially in TSV-last schemes, where extremely high silicon-to-oxide selectivity is required to preserve thin oxide liners [4].

TDVs introduce additional complexity due to the need to etch multilayer back-end-of-line dielectric stacks while maintaining uniformity and protecting underlying metallization [5]. Furthermore, intrinsically low dielectric-to-PR selectivity and limited HM options remain critical constraints.

Plasma dicing combines many of these challenges, requiring precise etching of silicon, dielectric, and polymer layers within a single process [6].

This presentation reviews current process solutions and innovations addressing these issues and highlights remaining gaps and future directions in plasma etching for advanced 3D interconnect integration.

References

[1] SJ. Koester, et al, IBM J Res Dev 52, 583–597 (2008).

[2] N. Matsubara, et al., 2012 4th ESTC, Amsterdam, Netherlands.

[3] WW. Shen, KN. Chen, Nanoscale Res Lett 12, 56 (2017).

[4] T. Shigetoshi, et al, VLSI 2026, Honolulu, Hawaii, accepted.

[5] Y. Morikawa and W. Chen, 2024 IEEE 74th ECTC, Denver, CO, USA.

[6] V. Georgieva, et al, 2024 SSDM, Himeji, Japan.

This work has been enabled in part by the NanoIC pilot line (nanoic-project.eu).

Through-silicon vias (TSVs) are crucial components for three-dimensional (3D) integration technologies. Conventional Bosch processes typically rely on fluorinated gases such as c-C₄F₈ and SF₆, which exhibit high global warming potentials (GWPs) and are increasingly subject to environmental regulations. Given the criticality of deep-Si etch processes for packaging applications, it is of great interest to investigate alternative plasma chemistries to focus on sustainability for future technological node development.

In this work, the applicability of alternative with much lower GWPs for TSV applications at aspect ratios >10:1 with different integration routes, is investigated. The alternative gases show comparable etch profiles to the conventional C₄F₈-SF₆ processes – key performance indices including critical dimensions (CD), anisotropy, etch rates, mask selectivity are compared. Optical emission spectroscopy (OES) is used to assess gas phase species and compare plasma characteristics. Electrical characterization of the integrated TSVs shows similar resistance scaling for C₄F₈-SF₆ processes and alternative gases, with performance governed by TSV geometry, CD, and liner material properties. Exhaust sampling analysis using Fourier Transform Infrared Spectroscopy (FTIR) showed a two to three orders of magnitude reduction in high-GWP emission byproducts with the usage of alternative gases compared to C₄F₈ and SF₆. These results demonstrate a viable alternative pathway to reducing environmental impact while maintaining etch and electrical performance integrity for TSV fabrication.

Deep silicon etching is a major challenge for the development of many electronic devices, such as DRAM memories, integrated 3D capacitors, and MEMS. Developing deep silicon etching processes with minimal morphological defects and a high degree of anisotropy, while avoiding empirical trial-and-error approaches, remains a significant scientific and technological challenge requiring substantial time and resources.

The Bosch process, based on an alternating discharge including an etching phase and a deposition phase, appears to be a particularly suitable solution for meeting these requirements depending on the targeted applications. However, its optimization generally requires long and costly experimental campaigns.

In this context, the development of etching simulators based on a multi-scale approach represents a promising alternative. Such tools could contribute in the understanding of plasma–surface interaction mechanisms and the optimization of the etching processes in a faster time.

In this context, we developed a multiscale approach for a deep silicon etching using the Bosch process with alternating discharges SF₆ for the etching step and C₄F₈ for the deposition step.The model is composed of three modules: a global kinetic model of SF₆ and C₄F₈ ICP plasmas, a sheath model based on the Monte Carlo method, and a 2D etching model based on the cellular Monte Carlo method.The simulator allows the prediction of the temporal evolution of the etched profiles, the surface chemical composition, and the etching rate.Well-known phenomena in the Bosch process, such as scalloping and undercut, are clearly demonstrated.

One of the disadvantages of our multi-physics models is its very long run time.Using machine learning to predict the evolution of silicon etch profiles as a function of the operating conditions (RF power, pressure, gas flow rates, …) is a good way to significantly reduce the simulation times.The simulations from our multiscale approach serve as training data for the machine learning. This enables to move towards an AI approach that contributes to Bosch process optimization.

High aspect ratio plasma etching of Si for TSV (through-silicon vias) and packaging applications is primarily performed in fluorine-containing plasmas with feedstock gases containing CF₄, NF₃ and SF₆ [1]. Si etching by F atoms is an isotropic process. Adding gases such as O₂ and SiF₄ produces sidewall passivation which, with moderate substrate biases, enables anisotropy. For comparable F-atom fluxes to the wafer, several studies have reported significantly higher Si etch rates in SF₆-containing plasmas compared to other F-containing plasmas [2]. This enhancement has been attributed to the possible catalytic role of S-containing species, surface sulfidization, which increases the efficiency of fluorination and increases etch yields [1,3]. In this work, results will be discussed from feature-scale modeling of Si HAR etching in an inductively coupled plasma (ICP) source sustained in SF₆/O₂/SiF₄ gas mixtures. With the goal of distinguishing the unique aspects of plasma etching in gas mixtures containing SF₆, the surface reaction mechanism includes fluorination, sulfidization, oxidation, and ion sputtering. Reaction probabilities were calibrated against experimental results obtained for different ICP powers, RF bias powers, gas compositions, and pressures. Reactor-scale simulations were performed with the Hybrid Plasma Equipment Model (HPEM), and feature-profile evolution was evaluated using the Monte Carlo Feature Profile Model (MCFPM) [4]. The consequences of plasma properties on feature evolution will be discussed. A brief update on the gas phase reaction mechanism for SF₆ containing plasmas will be provided.

This work was supported by ULVAC, Inc.

References

1. P. Arora et al., J. Vac. Sci. Technol. A 37, 061303 (2019).
2. V. M. Donnelly et al., J. Vac. Sci. Technol. A 35, 05C202 (2017).
3. P. Y. Tessier et al., Nucl. Instrum. Methods Phys. Res. B 155, 280 (1999).
4. C. Huard et al., J. Vac. Sci. Tech. A 35, 05C301 (2017).

This study presents a quantitative investigation of the bowing mechanism observed in high-aspect-ratio (HAR) silicon etching using SF6/O2 inductively coupled plasmas through a multi-scale simulation framework. By integrating reactor-scale plasma modeling with feature-scale profile evolution analysis, we examine the dynamic balance of reactive radicals at the etch front and its role in profile formation. In contrast to previous studies relying on qualitative interpretations based on optical emission intensity ratios, this work provides numerical validation of the transport gradient model.

The model demonstrates that the localized oxygen-to-fluorine (O/F) flux ratio, rather than the global gas composition, governs sidewall passivation and etch stability. The local flux ratio incorporates transport physics, including Knudsen diffusion and surface sticking probabilities, which significantly modify reactant distributions. Consequently, gradients in radical flux develop along trench depth, producing spatially varying surface reactions.

Parametric simulations identify a critical threshold in the local O/F flux ratio between 3.5% and 3.6%. Above this threshold, oxygen-rich coverage enables passivation and anisotropic etching. Below it, fluorine-dominant coverage induces a nonlinear increase in etch rate, causing rapid lateral etching and bowing.

This insight explains why a 30% O2 condition maintains verticality at shallow depths, whereas 20% O2 causes immediate bowing as the local O/F ratio falls below the threshold. These findings highlight the importance of transport-limited effects in HAR structures and provide a theoretical basis for optimizing radical flux control in advanced plasma etching processes.

Chalcogenide materials are alloys composed of one or multiple chalcogen elements (S, Se, Te) and one or multiple alloying elements (Ge, As, …). They demonstrate a wide transparency window and high linear and non-linear (NL) indices in the near and mid infrared. Some of them exhibit phase-change properties, transitioning reversibly from an amorphous to a crystalline state, with an unusual contrast between the electrical and optical properties of these two states [1,2]. As their properties makes them interesting for micro and nano-photonics applications, one issue impeding their widespread integration is the ability to pattern them without altering their optical properties.[3]

To address this issue, a plasma etching process with minimal impact over morphology and stoichiometry is needed for GeSe_xTe_1-x destined to reconfigurable (1.55µm) and NL (2µm) applications. A focus will be made on HBr/H₂ etching gases and H₂/Ar Post-Etching Treatment (PET), expecting low impact on surface roughness (Rq), stoichiometry alteration and non-volatile compound (NVC) formation.[4]

This work involves unpatterned Ge₅₀Te₅₀ and Ge₅₀Se₅₀ thin film etching with HBr and HBr/H₂ both with and without PET in an ICP chamber. Characterization methods such as 2D Atomic Force Microscopy (AFM) for Rq and X-Ray Photoelectron Spectroscopy (XPS) for atomic composition were used. Figure 1 shows AFM measurement of Rq for both alloys at each gas composition. HBr/H₂ mix induces the lowest Rq and PET decreases Rq for both alloys. Figure 2 shows XPS measurement of both alloys with each gas composition. HBr and H₂ cause stoichiometric shifts by forming volatile GeH_x and NVC GeBr_x in both alloys. For GeTe, PET seems to limit both NVC and volatile by-products. For GeSe, PET induces volatile SeH_x by-products generation.[5] We can conclude that HBr/H₂ + PET etching mix seems the most promising.

To go further, the impact of HBr/H₂ + PET mix over unpatterned and patterned GeSe_xTe_1-x thin films will be studied. Characterizations techniques as 3D and 2D AFM for sidewall roughness and Rq measurement, XPS for atomic composition and Scanning Electron Microscopy (SEM) for sidewall angle analysis will be used. The addition of CH₄ gas into the etching mixture could be studied to improve sidewall angle control.[6]

[1] A. Albanese, Physica Rapid Research Ltrs 2400129 (2024)

[2] P. Noé, Semicond. Sci. Technol. 33, 1 (2017)

[3] B. J. Eggleton, Nature Photon, vol. 5, no. 3, pp. 141–148, Mar. 2011

[4] B. Fontaine, ‘Mechanism of residues formation on Ge-rich GST after plasma etching’

[5] D. R. Lide, “Handbook of Chemistry and Physics”

[6] K. T. Vu JVST: Vacuum, Surfaces, and Films, vol. 29, no. 1, Art. no. 1, Jan. 2011