AVS2009 Session PS1-TuM: Advanced FEOL and BEOL Etch

The pace at which microelectronics technology is progressing is highly challenging with conventional device architecture. The stringent and conflicting requirements in microelectronics for damage-free plasma etching processes, with improved uniformity, higher selectivity, better anisotropy, more precise ion energies/fluxes control and enhanced process throughput have stimulated an intensive research effort among academic and industrial communities. This research is focused on novel approaches for the design/control of the next generation of plasma processing reactors. Following the above challenges, the dry etch process regime for gate etching has moved towards low pressure plasmas with higher densities. In this regime, the risk of plasma induced damage(PID) or charging damage increases, potentially affecting the overall device electrical performance. PID includes UV damage and highly energetic ion bombardment damage. Moreover, for high aspect ratio structures, electron shading effect becomes more dominant enhancing the risk of charging damage. In the past, it was demonstrated that pulsed radio frequency(PRF) inductively coupled plasmas(ICP) have the promise to address some of the above challenges. Typical commercial ICP reactors consists of 2 RF power supplies, the RF source which is fed to the antenna coils of the ICP source and RF bias applied to the substrate. Accordingly, 3 main different regimes of operation for pulsed plasmas might take place. The first, known as source pulsing, in which the source is operating in PRF mode while having the bias in continuous wave(CW) mode. The second is bias pulsing i.e. source in CW mode while the bias is in PRF mode. The third one is synchronized pulsing, for which both source and bias are pulsed simultaneously at the same frequency and duty cycle.

Recently we have evaluated the impact of synchronized pulsing plasma on gate etch for sub-50nm DRAM applications. The evaluation included basic etching characteristics such as average etch rate, uniformity and selectivity, 35nm gate critical dimension(CD) uniformity and profile control, and plasma induced damage. It was demonstrated that by control of the synchronous pulse parameters extends the plasma operating conditions range aiming to improve processes for finer features. In particular, we have shown gate CD controllability, PID mitigation, and significant reduction in electron shading effect and in the gate leakage current along with improving the electrical performance of the overall device. 2D plasma and feature scale modeling results will be used to illustrate the basic physics of synchronous pulsing, in particular its effect on the ion energy distribution.

Plasma etching processes for microelectronics fabrication at future technological nodes are extremely challenging. The requirements regarding the uniformity (both etch rate and critical dimensions) are also more stringent than ever. One particular challenge in plasma etching of extremely high aspect ratio features (aspect ratio > 40) is minimizing plasma induced damage, both physical and electrical. The via-like features may physically twist/turn due to the stochastic nature of fluxes entering the feature as the size of the opening shrinks.[1] Charge trapped by the polymer on the sidewalls exaggerates this phenomenon. Alternately, charge retention at the bottom of trenches may lead to breakdown as the material stresses under the accumulated charge creating a weak path for the injected current.[2] Pulsed plasma operation has been shown to be a promising approach to improving uniformity while reducing charge damage.[3] Although pulsing of both capacitively and inductively coupled plasma sources has been investigated before, novel pulsing schemes such as synchronous pulsing in multi-frequency capacitively coupled plasmas (CCP) may allow for expanded operating regime for damage-free etching of high aspect ratio features.

In this paper, pulsed and continuous plasma operation of a multiple frequency capacitive coupled plasma reactor in electronegative gas mixtures will be discussed using results from a computational investigation. A 2/3-dimensional plasma equipment model (CRTRS) [4] has been linked to a Monte Carlo feature profile model [5] to assess the consequences of pulsed plasma operation on etching of dielectric features. Results will be discussed for impact of pulse characteristics such as duty cycle, pulse excitation frequency, phase lag between source and bias pulses on dielectric etching in a multi-frequency CCP chamber. Careful tailoring of pulsing at both source and bias frequencies enables negative charge acceleration in the features and helps negate charge buildup. The impact of varying plasma electronegativity at different gas pressures will also be discussed. If strongly electronegative gas mixtures are used, sustaining a steady pulsed plasma can however be complicated as the plasma may not re-ignite after power is turned-off.

¹ A. Agarwal, M.M. Wang, and M.J. Kushner, 54^th AVS Symposium 2007.

² T. Ohmori and T. Makabe, Appl. Surf. Sci. 254, 3696 (2008).

³ S. Banna, et al., 55^th AVS Symposium 2008.

⁴ A. Agarwal, P.J. Stout, S. Rauf and K. Collins, 61^st Gaseous Electronics Conference 2008.

⁵ P. Stout, 60^th Gaseous Electronics Conference 2007.

With the continuous scaling down of semiconductor device dimensions, the linewidth roughness (LWR) becomes a non negligible parameter that needs to be controlled in the nanometer range for the future technological nodes (1.7nm (3σ) for the 32 nm technological node). In previous studies, we demonstrated that the 193 nm photoresist mask LWR is the main contributor to the final gate LWR. We also observe that the LWR is mainly decreased during the plasma etching steps in which the resist mask is involved (BARC and hard mask etching). Preliminary conclusion is that the photoresist mask is the first vector of LWR decrease during plasma exposure. The resist LWR is therefore the key parameter to sucessfully control the final metal gate LWR in the nanometer range. In the present study, we first evaluate the impact of HBr cure plasma treatment and resist trimming processes on the resist LWR and second analyze how these plasma etching steps impact the final gate LWR. LWR measurements are performed using the CD-AFM technique much more powerful than commonly used CD-SEM. First results indicate that both resist trimming and plasma cure treatment processes improve the resist LWR and consequently the final gate LWR. We demonstrate that, during cure processes, plasma Vacuum UltraViolet (VUV) light is mainly responsible for the resist LWR decrease while during trim processes, the plasma VUV light combined to the lateral erosion of the resist induced by reactive radicals is identified as the main contributor to the resist LWR decrease.

However, we also show that the sequence of cure and trim processes has a less important impact on the gate LWR than a cure or a trim process only and that the position of the cure treatment in the sequence of plasma etching steps involved in the gate patterning process has some consequences in the final gate LWR. Finally, as the etching mask used to pattern the gate plays a primordial role in the final gate LWR, we compare the impact of two masking strategies: one using amorphous carbon layer as etching mask and the other one a spin on carbon hard mask.

As the design rule of ULSI devices continue to be scaled down, the critical dimension (CD), CD bias, and the mask profile control technique has been needed. As the result of this study, precise CD control of multilayer mask etching was established by RLSA (Radial Line Slot Antenna) microwave plasma source. The multilayer stack which was used for experiments consisted of Photo Resist/SiARC/Organic/SiN/Si-substrate.

The results are: first, zero Iso/Nest bias was accomplished. As result, the same CD bias is obtained kept in both the Iso and Nest pattern with vertical profile. Second, CD Bias is controlled in the range of several +/- nm with same bias of Iso/Nest by adjusting SiARC etching condition. By these characteristics, it is possible to make hard mask CD same as patterned resist CD in any pattern density.

These results are obtained by RLSA micro-wave plasma characteristics. RLSA generates high density plasma just below top dielectric plate, and as the plasma diffuses forward the wafer, its density and electron temperature become lower by diffusion. The etched by-products do not re-dissociate and not deposit on the wafer in the low electron temperature condition. This result shows that this plasma can etch only biased ion direction without side-wall deposition.

These unique characteristic will remove the burden of adjusting the width in the patterning step.

The continued scaling in semiconductor industry provides new challenges for etching Shallow Trench Isolation (STI) features to create active area islands. Control of the STI profile is of primary importance, e.g. trench angle control of 88^o ± 0.2^o being requested across a 300 mm wafer, along with the additional demand to control the trench depth range non-uniformity to <2.5%, for ~2500-3000 Å trench depth. Typically, the stringent profile control requirements are met by operating halogen based Transformer Coupled Plasma (TCP^TM) plasmas in the mid-pressure operating regime, 20mT to 60mT. However, in this regime the trench depth non-uniformity is upward of 5% and has a characteristic wafer pattern that resembles a “donut”, which is due to the electron mean free path, λ_mfp, being short (e.g. 0.85cm for 20mT Cl2) compared to the chamber dimensions. The electrons and ions are predominately produced in the TCP’s torroidal power deposition region, with the torroid pattern then being transferred to the wafer plane through ion diffusion. The trench depth pattern can be substantially reduced by operating at lower pressure <5mT, such that the λ_mfp is comparable to the chamber dimensions and energized electrons can ionize neutrals with almost equal efficiency across the chamber, where the shape of the plasma density determined only by ambipolar diffusion. However, this severely inhibits profile control with trench angle and selectivity requirements not being met.

This paper will discuss the work undertaken at Lam Research to characterize halogen plasma’s produced by the TCP configuration of a Kiyo^TM process chamber. Plasma diagnostic and simulation data shows that the plasma density uniformity can be substantially improved for a given pressure operation regime by optimizing the TCP hardware configuration. This optimization will translated into achieving <2.5% trench depth uniformity at mid pressure operation whilst maintaining profile control. Future challenges facing STI trench depth etch will also be discussed.