Papers

AVS1997 Session PS-MoM: Plasma Damage

Monday, October 20, 1997 8:20 AM in Room A7/8

Monday Morning

Start	Invited?	Item
8:20 AM		PS-MoM-1 Plasma Charging in ULSI Fabrication J.P. McVittie (Stanford University); T. Kinoshita (Kobe Steel, Japan); M. Joshi (Stanford University) Charging can cause both device damage and profile distortion, as such it is of increasing concern as device aspect ratios increase and gate oxide thickness decrease. The main causes for charging are equipment caused plasma nonuniformity and wafer caused topography dependent changing (TDC). Nonuniformities in electron temperature, plasma density and plasma potential cause surfaces to charge or conduct to bring the local ion and electron currents into balance. If the charging voltage is large enough excessive tunneling current can flow through gate oxide resulting in damage. This damage depends on many factors which include: the degree of nonuniformity, the plasma density, the device layout, the oxide quality, the gate exposure, the wafer temperature and current path back to the plasma. For nonuniformity caused charging, the ion trajectories are distorted by voltage differences on the surfaces which affect the field over a large fraction of the sheath. In TDC the problem is caused by the directional difference between positive ions and electrons which cause positive charging at structure bottoms and negative charging at structure tops. Although the field distortion is usually confined to within a few microns of the surface, both oxide damage and profile distortion can be caused by TDC. Except for the nonuniformity issues, the same factors affect TDC damage. Since the energy distributions of both the ions and electrons strongly affect TDC, this charging is reduced by lowing Te or increasing the low energy positive ion population. This charging is also reduced by pulse operation which can lower Te and allow negative ions to reach the surface. Experimental and simulated examples of charging for different conditions will be discussed in terms of damage and profile distortions during etching and deposition process steps.
9:00 AM		PS-MoM-3 The Physics of Plasma-Induced Charging Damage K.P. Giapis, G.S. Hwang (California Institute of Technology) As semiconductor manufacturing moves towards smaller logic devices and thinner gate-oxides, there is serious concern that pattern-dependent charging during plasma etching will impede progress by distorting etch profiles and by inducing catastrophic tunneling currents through gate-oxides. While profile irregularities have been minimized in the past by trial-and-error, the extraordinary complexity of plasma interactions with patterned semiconductor surfaces guarantees that the empirical approach will become rapidly limited by the time and cost of process development, thus emphasizing the need for fundamental understanding of the underlying physics. To that effect, we have developed a comprehensive theory of plasma-induced charging effects¹ which combines sheath dynamics, electrostatics, surface charging, electron tunneling, reactions, and scattering. Three different time-scales are bridged together by Monte Carlo techniques: electron tunneling (10^-7 s), microstructure charging (10^-3 s), and profile evolution during overetching (10² s). The simulations capture the asymmetric "notching" effect, the symmetric notching in electrically connected lines and the dependence of the notch extent on open area. The influence of various geometric parameters (aspect ratio, mask thickness)² and plasma parameters (electron temperature³, rf bias and frequency) on profile evolution is explained self-consistently and in agreement with reported experimental data. The importance of plasma chemistry through its influence on the salvage layer at the sidewall is revealed and offers insight into techniques for minimizing notching. The predictive value of our theory is demonstrated by predicting two new counter-intuitive effects: a) When the mask thickness is reduced, increased electron irradiation of the polysilicon sidewalls causes the line potentials to decrease, which perturbs the in-trench ion dynamics so that notching affects ALL lines, even when not electrically connected⁴; b) The use of ultrathin oxides (≤5 nm) will actually eliminate notching by enabling electron tunneling from the substrate to decrease surface charging potentials at the bottom of high aspect ratio trenches. The latter effect suggests new rules for microstructure layout. The talk will also address the issue of "electron shadowing" damage. Tunneling current transients through the oxide under various gates will be shown as a function of profile evolution during both the main etch and the overetch. The results identify the final clearing step at the bottom of trenches as the one during which most of the damage occurs, and suggest that minimizing RIE-lag will not solve the problem. Strategies for the reduction of electron shadowing damage will be proposed. The predictive nature of the simulations suggests that plasma-induced charging damage could be minimized by design. ¹G. S. Hwang and K. P. Giapis, J. Vac. Sci. Technol. B, Vol. 15, 70 (1997). ²G. S. Hwang and K. P. Giapis, J. Appl. Phys., Vol. 82, in press (July 15, 1997). ³G. S. Hwang and K. P. Giapis, J. Appl. Phys., Vol. 81, 3433 (1997). ⁴G. S. Hwang and K. P. Giapis, Appl. Phys. Lett., Vol. 70, 2377 (1997).
9:40 AM		PS-MoM-5 Plasma Measurements and Plasma Damage in a High-Density, Inductively Coupled Metal Etcher J.I. Colonell (Bell Laboratories, Lucent Technologies); M. Malyshev (Princeton University); N.A. Ciampa, V.M. Donnelly, A. Kornblit (Bell Laboratories, Lucent Technologies) As high density plasmas have been employed in more etching processes in semiconductor manufacturing, new mechanisms of plasma damage to the gate oxide have become important. We have evaluated the plasma damage due to metal etch in a Lam Alliance inductively coupled plasma metal etcher. The testers were 0.35 µm transistors (65 Å gate oxide) with large metal structures, which act as charge collection antennae, connected to the gate: the primary indication of plasma damage is antenna dependence of transistor parameters after Fowler-Nordheim stressing of the oxide. The damage is found to vary with the gap from the RF source antenna to the wafer, and is also sensitive to the aspect ratio of the metal pattern. The processing plasma has been characterized using both Langmuir probe and optical emission techniques. The dependence of the plasma density, uniformity, and potential on the gap change varies with source power, pressure, and chemistry. For standard metal etch conditions, a 10 mTorr Cl₂/BCl₃ plasma at a source power of 350 W, the nonuniformity (+/-%) improves from 12% to ~1% when the gap is increased from 10.2 to 13.2 cm, while the plasma density near the center of the wafer is constant. Optical emission measurements indicate that the electron temperature is independent of gap height. The correlation of these plasma measurements with the gate oxide damage data will be discussed with respect to the current theories of plasma damage, including electron shading and RIE lag.
10:00 AM		PS-MoM-6 Radiation Damage Effects in a High Density Plasma G. Bersuker, J. Werking, S. Anderson, Y.D. Chan (SEMATECH) In the present paper, we report the first comprehensive evaluation of UV effects in a commercially available HDP etch tool. The test structures consist of 0.35 gate-length NMOS and PMOS transistors with metal charge collecting antennas connected to their gates. The active area of some devices are covered by a metal-2 shield to prevent radiation exposure. We report results on devices with 40 Å, 50 Å, and 65 Å gate oxide thickness and antenna-to-gate ratios up to 90K:1, and on two plasma gases, C₂F₆ and O₂. The effects of radiation were measured by the difference in transistor parameter values taken on the same devices before and after exposure in the tool. The unshielded test show parameter shifts that depend linearly on the time of plasma exposure, independent from antenna ratio. Transistors with thicker gate oxides show less radiation induced degradation. Radiation effects exhibit strong dependence on plasma chemistry. The radiation induced parameter shift did not completely disappears following a 30 minute, 400 C anneal. Transconductance degradation following hot carrier stress correlates linearly with the parameter shifts and time of UV exposure. Consecutive re-exposure of devices without annealing show linear accumulation of UV induced damage with exposure time. When high damage was introduced into devices during the first exposure, we observed a partial annealing effect after the second exposure. We estimated the coefficient of UV quantum absorption by oxide to be 0.28 m^-1. Interface trap and area charge generation rates in transistors exposed to HDP were found to be about 0.8x10¹⁰ cm^-2 sec^-1 and 0.2x10¹⁰ cm^-2 sec^-1, respectively. To explain the observed UV annealing effect, we suggest that UV radiation causes hole generation in the oxide and electron injection to the gate oxide from Si. Within this model, the obtained data found their explanation with the electron injection rate and interface trap generation coefficient being of the order of 0.8x10¹² electron cm^-2 sec^-1, and 0.9x10^-2 trap/injected electron, respectively.
10:20 AM		PS-MoM-7 Pattern Dependent Wafer Charging in an Inductively Coupled Metal Etch System R. Patrick, P.L. Jones, S.C. Siu (Lam Research Corporation) Plasma charging damage is a major concern for all high density plasma generating equipment used in the microelectronics industry today. Methods of measuring charging potentials, such as CHARM^TM wafers or SPORT wafers have been used to investigate possible charging mechanisms. It has been found that pattern dependent charging or electron shading is generally dominant over other possible concerns such as plasma non-uniformity. Electron shading is a charging phenomenon caused by the interaction of a high density plasma with a high aspect-ratio patterned surface. A methodology has been developed in order to enhance the sensitivity of CHARM^TM and SPORT wafers to pattern-dependent charging. This involves adding a fine line resist pattern to the surface of the charge-collection electrodes (CCE) of these wafers in order to mimic the type of structure which might typically be found on a semiconductor device wafer. In addition an unpatterned SPORT wafer was used to monitor the plasma characteristics such as plasma density and electron temperature at the wafer surface as the hardware and process conditions were varied. These methods were used to characterize the charging characteristics of a commercial high density metal etch tool as a function of plasma condition. It was shown that the patterning effect greatly enhances the measured charging voltages for both Ar and BCl₃/Cl₂ plasmas, as well as the current densities collected by the CCE. The dc bias has a strong influence on the level of pattern-dependent charging. Reducing the overall plasma density results in a reduction in this pattern-dependent charging. Preliminary results also indicate an aspect ratio dependence to the charging voltage.
10:40 AM		PS-MoM-8 Reduction of Electron Shading Effect on Gate Etching using High Pressure HBr Gas Chemistry K. Yoshida, K. Tokashiki, H. Miyamoto (NEC Corporation, Japan) Recently, the electron shading effect has become a serious problem in etching processes using high-density low-pressure plasmas. In gate etching, this effect causes irregular notching profiles and/or gate oxide degradation. Furthermore, it can be expected that these problems will become severe in the fabrication of sub-quarter-micron devices because of their high aspect ratios. It has been reported that the time modulation, pulsed bias and low frequency bias plasmas are effective about in reducing electron shading effect. They are, however, complicated techniques and increase process cost. We found that in HBr gas plasma the notching problem was suppressed by applying high pressure(≥20mTorr) and low source power to the over etching step of 0.18 µm gate electrode. We used an inductively coupled plasma(ICP) and investigated etching characteristics of Cl₂ and HBr gas chemistries in this over etching step. It was found that in HBr gas plasma, high pressure and low source power were effective in improving the notching problem caused by electron shading effect. In Cl₂ gas plasma, however, the etching profile was not improved under these condition. This was caused by chemical reactivity difference between Si-Br and Si-Cl. High selectivity to SiO₂(about 100) was obtained in high pressure HBr gas plasma. Thus, we found that use of HBr gas plasma under high pressure and low source power to 0.18 µm gate etching was very effective in regards to reduction of electron shading effect on etching profile.
11:00 AM		PS-MoM-9 Mechanisms Involved in Plasma Charging Induced Device Damage V. Vahedi, N. Benjamin, A. Perry (Lam Research Corporation) We examine mechanisms for surface charging during plasma processing. The mechanisms include potential gradients driven by plasma non-uniformity, differential feature charging associated with surface topography, and current leakage into the external circuit. We derive an analytic model for the voltage drop across the gate oxide as a function of electron and ion shadowing, and compare this mechanism's relative importance for inducing device damage to that caused by plasma non-uniformity or external leakage. With the aid of computer simulation, our model predicts that under typical process conditions the shadowing mechanism can be the dominant cause of device charging. The charge dose delivered by the shadowing mechanism is shown to be consistent with the magnitude required for damage to devices.
11:20 AM		PS-MoM-10 Non-Contact Electrical Characterization of Plasma Damage I.J. Gupta (Texas Instruments); G.S. Horner (Keithley Instruments) Historically, full test chips and antenna monitors have been used to detect potentially damaging plasma conditions in semiconductor process equipment. These methods require specially processed wafers, but they have proved very useful for equipment evaluation and process optimization. Sensitive measurements, such as process-induced threshold voltage shifts, are well established as damage metrics. However, there is room for improvement in the ease of use and measurement turnaround time. Non-contact electrical measurements on unpatterned monitor wafers provide a means of rapidly obtaining established electrical test parameters without the need for expensive wafer preprocessing. In this paper, a newly released non-contact electrical characterization tool is used to 1) investigate a variety of plasma damage sources and 2) perform process optimization. Correlations are established between this technique and full device electrical testing. Case studies are presented in a) oxide leakage due to TEOS deposition, b) flood gun optimization for ion implants, c) dependence of oxide damage on poly etch magnetic field, d) HDP oxide deposition, e) oxide damage from photoresist ashers, f) sputter cleaning before metal deposition, and g) a non-plasma charging mechanism: oxide charging during spin rinse drying. Established electrical test parameters are used (Vfb, Dit, Qeff, Tox, oxide leakage) as well as a high speed surface voltage scanning technique. The important differences between plasma damage detection methods are reviewed. In particular, the role of two dimensional surface voltage mapping is described, and its distinct limitations are discussed. Flatband voltage measurements are shown to be both more quantitative and robust in several of the examples.
11:40 AM		PS-MoM-11 Observation of Channel Shortening in n-MOSFETs Arising from Interconnect Plasma Processing M.G. El Hassan, O.O. Awadelkarim (The Pennsylvania State University); J. Werking (Sematech) We have recently shown that metal 1 layout can play a major role in shaping the potential differences between n-MOSFET terminals during metal 1 plasma processing in such a way as to invoke degradation mechanisms other than conventional capacitive gate charging. This was shown by using specially-designed 0.5 micron n-MOSFET, referred to hereafter as device A. The source and gate metal pads of device A are connected together and the drain metal pad is floating. This device was shown to incur more damage compared to another test structure with discrete metal pads and a six times larger gate antenna ratio. Using charge pumping current ( I_CP ) measurement, the damage on device A was shown to comprise positive charge build up in oxide edge overlapping the drain. In this study, we further examine the damage observed on device A. A hot carrier stress ( HCS ) for 1 minute with V_g = V_d = 4 V (V_g is the gate voltage and V_d is the drain to substrate bias ) is seem to produce 20 % degradation in g_m of type A and no degradation in a control device ( a n-MOSFET similar to type except for all metal pads connected to the substrate during processing ). However, more importantly, the degradation in g_m is not accompanied by any change in the maximum of I_CP. Instead, a significant decrease in I_CP at the lower end of the gate pulse base level ( V_base ) sweep, which was chosen such that the device is under depletion or accumulation during the entire pulse, is observed . These observations unambiguously establish that : (1) the degradation of g_g in type A is not due to generation of interface states by the HCS for that would have resulted in an increase of the maximum of I_CP; (2) The decrease in I_CP at low V_base is attributable to neutralization of the positive charge in the drain edge with electrons injection during HCS. Based on the results we propose that the plasma-induced positive charge in the drain side of the gate oxide has resulted in the inversion of the channel at that side and, hence, channel shortening. g_m degradation in type A caused by HCS is, therefore, due to restoring the nominal channel length by the mechanism described in (2) above.