Papers

AVS1996 Session PS1-ThA: Etch III

Thursday, October 17, 1996 1:30 PM in Room 201C

Thursday Afternoon

Start	Invited?	Item
1:30 PM		PS1-ThA-1 Electroluminescence as an Indicator for "Soft-breakdown" in Thin Oxides Due to Plasma Processing M. Okandan, S. Fonash, O. Awadelkarim (Pennsylvania State University); J. Werking, G. Bersuker, Y. Chan (Sematech) Luminescence is used as a common tool in failure analysis to locate defective regions and in our study there are new aspects to the light emission observed from MOSFET gate areas :(1)devices used were sub half micron CMOS transistors with oxide thicknesses from 45 to 135A, (2)light emission is observed at the poly gate-bird's beak edge overlap, (3)only devices that had antennas designed for the contact etch step and were processed in a high density plasma etch system exhibit this luminescence, and (4)the presence of non-destructive luminescence correlates with the presence of oxide "soft-breakdown". We find that biasing conditions that put the channel into inversion and could also lead to impact ionization and subsequent recombination were needed to stimulate and maintain non-destructive light emission from the gate area. The source and drain of transistors had to be floating while the gate was biased to invert the substrate with a large voltage (Vg>15V). This electroluminescence occurred only in devices that had antennas and they exhibited current-voltage behavior we term "softbreakdown". Typical gate leakage current density (Jg) at operation voltage in transistors that exhibit gate luminescence is very large (nA/um\super 2\) in contrast to Jg of 1pA/um\super 2\ for control devices. These luminescent transistors with their large Jg values display a "soft-breakdown", all other transistor parameters, threshold voltage (Vth), transconductance (gm) and sub-threshold slope (S) are within 10% of those of control transistors. Also the luminescent transistors maintain their transistor characteristics (no change in Vth, gm or S) after the application of Fowler- Nordheim stress with a constant current in the ~100uA/um\super 2\. This electroluminescence and soft-breakdown are explained in terms of a model that assumes the generation of localized leakage paths induced in the gate oxide by the contact etching process.
1:50 PM		PS1-ThA-2 Direct Measurement of Charging Voltages and Currents S. Ma, J. McVittie (Stanford University) Wafer charging is still a concern for both damage and ion trajectory distortion during plasma processing. This paper discusses the use and design of an on-wafer real time probe to directly measure charging voltages and currents. Issues to be discussed include: a model for the charging J-V characteristic, the effect of probe layers on measurement, the factors which determine the substrate reference voltage, the effects of photoresist on charging, and influence of machine parameters such as reflect power on charging measurement. Experimental probe results will be presented for a variety of plasma conditions.
2:10 PM		PS1-ThA-3 Electrical-Stress Simulation of Plasma-Damage to Submicron MOSFETS: A Comparison between DC and AC Stresses L. Trabzon, O. Awadelkarim (Pennsylvania State University) Two mechanisms are currently acknowledged as responsible for the degradation of ultra-thin gate oxides and oxide/Si interfaces in MOSFETs during plasma processes. These two mechanisms are : (1) charging damage arising from Fowler-Nordheim (FN) dc cu rrent stress of the oxide and interface, and (2) particle bombardment damage which is due to the exposure of the oxide and interface at the gate perimeter to energetic particles. It has recently been reported, however, that plasma damage also comprises a third damage mechanism which involves ac stressing of the oxide and interface. The ac stress may originate from inductive coupling between time-varying magnetic fields and metal loops connecting gate and substrate/drain in one or several devices, or from spatial and time variation of electron and ion densities on the wafer surfaces during high-density plasma exposures. The study reported herein is aimed at establishing signatures of MOSFET damage induced by ac stressing applied at conditions that emulate plasma processing environment. We apply sinusoidal ac voltage stress signals to 0.5-microns n- or p-MOSFETs for durations that are typical of a plasma-etching unit process, and at amplitudes and frequencies that are compatible with plasma processing. We a ssess damage on MOSFETs by measuring transconductance, threshold voltage, and subthreshold swing. We find that the onset of damage to devices subjected to ac stressing occurs at voltage amplitudes as low as 4 V whereas in dc stressing, applied for the sam e time, damage becomes significant only at dc voltages larger than 10 V. We also show that damage from ac stressing attains a maximum at frequencies in the range 1 to 100 kHz and decreases at frequencies above 5 MHz. It is proposed that carrier hopping is primarily responsible for oxide current and, hence, device damage observed following the ac stress. This hopping current is insignificant during high-field dc stress when FN tunneling becomes the dominant conduction mechanism.
2:30 PM		PS1-ThA-4 Direct Measurement of Surface Discharging Currents during Plasma Etching W. Abdel-Ati, S. Ma, J. McVittie (Stanford University) Charging effects on damage and profile distortion, are becaming increasely important as device sizes decrease. An important issue in understanding charging is the role of discharging currents on the surface of a wafer which compete with the charging processes. In this work in-situ measurements where made on wafers of current flowing between the edges of poly-Si comb structures during actual plasma processing. For the case studied in an O/sub/2 plasma in a parallel plate etcher, it was found that the current driven by an external voltage had a threshold field of about 2E4 V/cm and an inverse dependence on the separation distance. In addition, the current increased with plasma power. The effect of this current path will be discussed in regard to the modeling and measurement of aspect ratio dependent charging.
2:50 PM		PS1-ThA-5 Mechanism of Halogen Etching of Cu Surfaces C. Nakakura, V. Phanse, G. Zheng, E. Altman (Yale University) The interaction of molecular halogens with single crystal and polycrystalline Cu surfaces was studied using temperature programmed desorption (TPD), low energy electron diffraction (LEED), and scanning tunneling microscopy (STM). Etching of Cu surfaces by Br\sub 2\ and Cl\sub 2\ were found to follow the same general mechanism: (1) reaction to form the Cu(I) halide followed by (2) sublimation of the halide layer. Linear growth of the Cu halides was observed independent of pressure, suggesting that the first step is adsorption rate limited over the range studied. The Br\sub 2\ on Cu(100) system exhibited two temperature effects on the formation rate of CuBr: (1) an irreversible increase in halide formation rate following annealing the chemisorbed layer of Br atoms and (2) a reversible decrease in halide formation rate as exposure temperature was increased. For Br\sub 2\ on polycrystalline Cu and Cl\sub 2\ on Cu(100), only the second effect was observed suggesting that it is a more general feature of oxidation reactions of metal surfaces. For the sublimation step, it was found that CuBr desorption rates could be increased above those expected from vapor pressure data by either limiting the thickness of CuBr films (formed by either reaction or vapor phase deposition of CuBr) on Cu(100) or by annealing the polycrystalline sample prior to exposure. This effect was only observed over a small CuBr coverage range for Cu(100), but persisted to higher coverages for polycrystalline Cu. In contrast, CuCl desorption was characterized by a single zero order peak with a heat of desorption matching the heat of sublimation of bulk CuCl independent of CuCl coverage. This difference makes Br\sub2\ a potentially more attractive etchant for Cu. The atomic-scale mechanisms responsible for the macroscopic behavior described above were characterized using STM.
3:10 PM		PS1-ThA-6 Minimizing Metal Etch Rate Pattern Sensitivity in a High Density Plasma Etcher C. Gabriel, J. Zheng (VLSI Technology, Inc.); S. Abraham (Lam Research Corp.) The dependence of metal etch rate on spacing between metal lines is a commonly observed phenomenon when space width shrinks to deep submicron dimensions [1,2]. We have measured this effect from SEM micrographs of TiN/Al-0.5%Cu/TiN wafers etched in a high density inductively coupled plasma metal etcher and identified that it is primarily an aspect ratio dependent etch effect because of its strong dependence on mask thickness. Further experiments have quantified the role of gas mixture and gas additives. Addition of 15% CHF\sub 3\ to a BCl\sub 3\/Cl\sub 2\ mixture resulted in a 50% reduction of the effect, and addition of both CHF\sub 3\ and Ar under particular process conditions resulted in almost complete reduction or even inversion of the effect. To understand the mechanism at work, we compared etching of metal and silicon, using the same BCl\sub 3\/Cl\sub 2\ chemistry for both films. In contrast to metal etch results, very little reduction in silicon etch rate was observed as spacing was narrowed. We propose a mechanism to account for our observations: neutral etchants with high sticking coefficient on aluminum appear to restrict etch rate in high aspect ratio structures. Similar structures on silicon do not experience such a restriction because silicon etch rate is limited by neutral etchants with very low sticking coefficient on silicon. Thus, addition of sidewall passivants (like CHF\sub 3\) which promote formation of polymer on the aluminum sidewall should decrease the sticking coefficient of neutral etchants and reduce the dependence of etch rate on aspect ratio. This mechanism agrees well with our data. ______ 1. R. Christie et al., IEEE/SEMI Adv. Semicond. Manuf. Conf., 224 (1994). 2. C. Gabriel and J. Zheng, to be published in Proc. 11th Symp. Plasma Processing, Electrochemical Society, Pennington, NJ (1996).
3:30 PM		PS1-ThA-7 Characterization of Pit-like Sidewall Corrosion in the Etching Process of Al-Cu Alloy I. Baik, K. Shin, J. Kim, W. Lee, C. Ko (Hyundai Electronics, Korea) The capability of interconnecting material patterning and the resistance to electromigration (EM) and stress migration (SM) of interconnecting metal lines should be required to the reliability of ULSI devices having multilevel metallization scheme more and more. The addition of a small amount of copper in Al alloys gives a solution to enhance the migration resistance, but it increases the difficulty of etching process due to the generation of non-volatile by-products and the corrosive properties of copper. We have observed the pit-like sidewall corrosion phenomena in the Al-Cu alloy lines after ECR metal etching process, which have been mainly occurred at the grain boundaries and the interface between Al-Cu alloy and barrier metal (Ti/TiN), and which might be expected as a detrimental factor on the device reliability. In this work, the effect of the pit-like sidewall corrosion on the metal life time has been evaluated using the stress test according to the degree of the corrosion. The cause and the preventive method of the corrosion from the various process condition such as metal main etching process, photoresist ashing process, metal line cleaning process, and metal alloy sputtering process have been studied using optical emission spectroscopy (OES), XRD, AES and SEM. The results of this work showed that the pit-like corrosion comes from the existence of Cu in Al alloy which acts as the ignition source of aluminum corrosion. The position and the size of pit-like corrosion in the lines of Al-Cu alloy might be influenced by the distribution of copper under the same etching condition.
3:50 PM		PS1-ThA-8 Performance of Different Etch Chemistries on Titanium Nitride Arc Layer and Related Selectivity and Microloading Improvements for Submicron Geometries on a High Density Metal Etcher S. Abraham (Lam Research Corporation) Different etch chemistries were tried to etch TiN ARC layer for the current study. A metal etcher with a high density plasma source was employed for the purpose. A standard stack of TiN ARC, Aluminum alloys with Copper\Silicon as the underlying layer and TiN as the barrier layer were used as the composite film structure, Titanium nitride and aluminum layers alone were used for the various characterizations of the process. Conventional BCl\sub 3\Cl\sub 2 chemistry was used initially to etch both the TiN ARC layer and the underlying Aluminum layer. Performance of BCl\sub3\Cl\sub 2\ chemistry on TiN ARC layer as well as on composite stack is evaluated. Partial etch measurements were taken to calculate the composite. Different etch chemistries were then employed for the ARC layer while keeping conventional BCl\sub 3\Cl\sub 2\ chemistry for aluminum layer. Different process performances were evaluated. Fluorine additives along with the Chlorine as the main etchant gave very high etch rate values to TiN layer. When TiN layer was etched with chemistries having faster etch rates, a remarkable improvement in the composite microloading was observed compared to the microloading values obtained with standard conventional chemistry. An improved etch rate uniformity was another noticeable performance obtained. Possible mechanism for this trend is explained in this paper. The experimental portion will explain the details regarding the etcher and the film structure used for the study, the results and discussion part will be giving the details of the process performance and a comparative evaluation of different TiN chemistries, possible mechanism for the trends observed, etc.
4:10 PM		PS1-ThA-9 Modeling and Profile Simulation of Aspect Ratio Dependent Metal Etching in an Inductively Coupled Plasma Etcher J. Zheng, C. Gabriel, S. Alibeik (VLSI Technology, Inc.); J. McVittie (Stanford University); S. Abraham (Lam Research Corporation) From the extensive experiments [1,2] we have carried out to quantify the effect of aspect ratio dependent etch (ARDE) rate on TiN/AlCu/TiN etching, the following facts have been collected: 1) the effect is more prominent in high density metal etchers; 2) the effect is reduced with higher pressure; 3) the effect becomes stronger with thicker mask; 4) forward and reverse lag co-exist; 5) polymer forming gas additives significantly reduce or even invert the effect; and 6) the effect is barely seen in silicon etched with identical processes. These facts lead us to conclude that the ARDE of the aluminum stack is related to neutral transport into the microstructures on the wafer, and that there are at least two competing neutral species which limit the etching in different regimes. Based on the experiments, we have modeled the aluminum ARDE effect using an ion-neutral synergy model based on Langmuir adsorption kinetics where neutral etchants and inhibitors are competing over surface sites [3-5]. This model cannot be fully correlated with experiments without correct calculation of the instant fluxes on the aluminum surface, which changes as profile and aspect ratio evolve. The Stanford etching and deposition profile simulator, SPEEDIE, is incorporated in the modeling for that purpose. The simulation results not only support our speculation but also lead to further understanding of likely species composition and their behavior and reactions in the inductively coupled plasma metal etcher. 1. C. Gabriel and J. Zheng, to be published in Proc. 11th Symp. Plasma Processing, ECS, Pennington, NJ (1996). 2. C.T. Gabriel, J. Zheng, and S.C. Abraham, abstract submitted for this symposium. 3. J. Zheng and J.P. McVittie, IEEE NUPAD-V, 37 (1994). 4. J. Han et al., J. Vac. Sci. Technol., B 13(4), 1893 (1995). 5. A. D. Bailey et al., J. Vac. Sci. Technol., B 13(1), 92 (1995).
4:30 PM		PS1-ThA-10 Loading Effect Reduction in Tungsten Etchback using SF\sub 5\Helicon Plasma C. Choi, Y. Seol, K. Baik (Hyundai Electronics Ind., Co., Korea) The mechanism of loading effect reduction has been investigated into tungsten etchback for sub-half micron tungsten plug using the SF\sub6\helicon plasma. In order to investigate the mechanism for loading effect, concentrations of gas-phase and surface species related to W and Ti were measured by using optical emission spectroscopy and secondary ion mass spectrometry. The loading effect defined as the etch rate ratio of W plug to bulk W film was observed by comparing materials of glue layer and etching parameters. Siliconoxide glue layer suppresses the loading effect better than does the TiN glue layer. The contact profile also gives an effect on the reduction of loading effect: a wine glass contact profile, formed from the previous wet etching of siliconoxide contact hole, can cause an effective redeposition of sputtered by-products of TiN\sub x\F\sub y\ (x and y \>=\ 0) leading to the suppression of tungsten plug loss. It can be explained by the fact that the normalized intensity of optical emission of Ti atom has shown a lower value for a wine glass contact than all dry contact in the case of TiN glue layer. In view of the bias power and electrode temperature, loading effect is decreased with increasing the bias power and lowering the electrode temperature. The intensity of Ti atom has also correlated with bias power and electrode temperature. In conclusion, the loading effect can be suppressed by enhancing the sputter yields for glue layer materials and the redeposition rate of non-volatile products.