Papers

AVS1996 Session MS-TuM: Issues in Integrated Circuit Manufacturing: Competitiveness for the R&D Community

Tuesday, October 15, 1996 8:40 AM in Room 201A

Tuesday Morning

Start	Invited?	Item
8:40 AM		MS-TuM-2 Prospects for Maintaining the Historical Reduction in Cost/Productivity J. Owens (Sematech) For twenty years or so, the semiconductor industry has maintained a 20-30% annual reduction in device cost per function. This impressive yearly reduction in cost per function helped put new and more advanced electronic products on the market at prices the consumer could afford. Thus, both the electronics and the semiconductor industries prospered in most of those twenty years. Unfortunately, the laws of economics and physics dictate that this impressive cost reduction cannot continue forever. We know that eventually technology barriers, the rising cost of research and development, the tremendous expense of capital investments, or some combination of the three will block our path. Traditionally, we have maintained cost reductions by shrinking feature sizes, increasing yields, moving to larger wafer sizes and improving other productivity factors--chief among them, improvements to equipment productivity. For the next several years, we can still count on the same annual cost improvements from shrinking feature sizes. However, yield improvements now occur rapidly and top out at above 90%, leaving little more room for improvement. Meanwhile, it is taking us longer to move from one wafer size to another so that the cost benefit is spread out over more years, reducing the annual cost benefits. The one area we have left with room for significant improvement is the area of equipment productivity.
9:20 AM		MS-TuM-4 Technology Deployment and the National R&D Infrastructure P. Peercy (Semi/Sematech) Since its inception, the semiconductor industry has relied on the central research laboratories in large, vertically integrated companies. Much of the research and many of the consequent technology advances required to drive the remarkable productivity growth of the industry came from these laboratories. About 15 years ago, the industry joined together to form the SRC to increase university funding to insure the continued supply of well-trained scientists and engineers as well as new concepts for the industry. Recent structural changes in the industry have fundamentally changed the R&D infrastructure which the semiconductor industry and its supplier infrastructure have relied upon. Central research laboratories have either been significantly decreased in size or changed in research and development emphasis from processing equipment and technology to areas such as software and systems. These changes leave a void in the nation's semiconductor science and technology infrastructure in both research and technology deployment. The semiconductor industry needs to ensure adequate financial support for long-term research in physical and chemical sciences and engineering to provide the new research concepts. A healthy university system to provide a continuing supply of well-trained scientists and engineers must also be maintained. For the nation to benefit from these investments, a method must be devised for effective conversion of research concepts into technology. This technology deployment will require well-defined processes and locations to mature research concepts. Since research advances will increasingly come to the semiconductor manufacturing industry through equipment and processes provided by the supplier industry, the industry will rely increasingly on the supplier industry for technology development and deployment. In addition to industry, major potential contributors are universities and national laboratories. After briefly reviewing the historical context, approaches to address the R&D infrastructure needs and bridging the technology gap will be discussed.
10:00 AM		MS-TuM-6 Contamination Control Challenges for ULSI Manufacturing T. Hattori (Sony Corporation, Japan) Of the many potential contamination sources, particle contamination generated within vacuum process equipment is the most frequent cause of yield loss in the manufacture of modern semiconductor devices. As the devices continue to be highly integrated and their geometries shrink while both die and wafer sizes grow, not only particulate contaminants but also metallic and molecular (or organic) contaminants adsorbing onto the surface of silicon wafers will have an increasing detrimental impact on both the performance and yield of the semiconductor products. Therefore, it becomes more important to detect these contaminants and to identify the sources in order to eliminate or at least reduce them from the wafer surfaces. Ultraclean requirements for next and future generation ULSI manufacturing will be further tightened. This presentation will focus on the detection and elimination of particulate, metallic, and organic contaminants on the wafers, with emphasis on the importance of rigorous wafer cleaning and preferable total contamination prevention systems development from the viewpoint of silicon surface cleanliness as the no. 1 priority. Some paradigm shifts will also be discussed, which will create future challenges and opportunities in contamination control engineering.
10:40 AM		MS-TuM-8 Research Infrastructure: What Is the Role of Universities? R. Reif (Massachusetts Institute of Technology) When asked what the role of research universities is in the most general sense, most of us would agree that it is best summarized by two key elements: (i) Education (i.e., human resources, textbooks), and (ii) Generation of Ideas and Knowledge. The latter would include ideas and knowledge to support existing industry, as well as the ideas and knowledge needed to create new industries. Recently, however, universities are being asked to play a greater role in our research infrastructure. Indeed, in the microlectronics community, it may be necessary for the universities to play a stronger role. The latter has been sometimes identified as the active participation in the creation of solutions for the critical problems the industry will face in the future. However, it is becoming more difficult for university facilities to carry out the critical process technology work required by industry. Academic wafer sizes will not be moving into 200 mm in the foreseeable future (let alone 300 mm wafers!), and very few academic facilities have the equipment base needed to work on and/or develop 0.1 micron process technologies. So how could universities play a bigger role? Should they? This talk will present one point of view (in academia, there are almost as many points of view as there are professors...). Types of university research will be discussed, and a proposal on how university research could play a stronger role without jeopardizing the two key elements we do best will be presented. The latter includes the concepts of linking university microfabrication facilities and creating University Networks of Excellence.
11:20 AM		MS-TuM-10 Key Challenges for 300mm IC Manufacturing Equipment B. Vasquez (Motorola) A growing number of IC manufacturers have announced plans to build 300mm wafer fabs or pilot lines before the year 2000, driven by the economies of scale provided by the larger wafer size. A minimum requirement for success is the simultaneous availability of a full suite of 300mm process & metrology tools. Many equipment suppliers are aggressively pursuing 300mm tool development programs with schedules to support the IC industry's timing for conversion. This paper will discuss the challenges facing both IC makers and tools suppliers in the convergence of 300mm wafer manufacturing and 0.25/0.18 micron IC technology. One of the key challenges in the wafer size conversion is tool throughput. For 300mm fab design, initial targets relative to 200mm fabs include the same capacity (wfrs/wk) in the same size fab. The challenge to equipment suppliers is to develop 300mm tools with >= 200mm tool throughput (wfrs/hr/sq m footprint). Using vacuum tools as an example, the wafer area increase of 2.25x over 200mm requires ~2x increase in chamber size. However, learning from 200mm plus creative 300mm tool design are being applied to hit the throughput target. Most of the early adopters of 300mm will design their fabs for 0.25micron ICs, extendible to 0.18micron. One of the key challenges in fab and tool design is the implementation of mini environments (ME). Equipment suppliers must build integrated MEs into each tool and implement tool interfaces and wafer handling systems compatible with 300mm ME wafer carriers. The target is a wafer environment 1 - 2 orders of magnitude better than the cleanliness of the fab environment to support the yield required for 0.25/0.18micron technology. Using vacuum tools again as an example, the combined requirements of tool throughput and ME integration have driven creative solutions for cassetteless transfer of the entire lot of 300mm wafers into the loadlock. These and other critical issues for the successful conversion to 300mm will be highlighted.