AVS1996 Session EM-WeM: Technology Challenges Beyond 0.1 micron ULSI

Wednesday, October 16, 1996 8:20 AM in Room 204A

Wednesday Morning

Start	Invited?	Item
8:20 AM	Invited	EM-WeM-1 Physical Limits on Nanoelectronics J. Meindl (Georgia Institute of Technology) Since 1960, microelectronics has advanced at a pace unmatched in technological history. Minimum feature size has declined by about a factor of 1/100, switching energy of a binary transition has decreased by approximately 1/10\super 5\ , the number of transistors per chip has multiplied by 10\super 8\ and the number of interconnect elements (i.e. minimum feature lengths of interconnect) per chip has increased by a factor greater than 10\super 9\. The central thesis of this discussion is that future opportunities for nanoelectronics, characterized by sub-100 nanometer minimum feature sizes and multi-billions of transistors per chip, will be governed by a hierarchy of physical limits. The levels of this hierarchy can be codified as 1) fundamental, 2) material, 3) device, 4) circuit and 5) system. Three key fundamental limits are derived from thermodynamics, quantum mechanics and electromagnetics. The most important material limits include constraints on switching energy, carrier transit time and heat removal capacity imposed by a semiconductor and a time-of-flight constraint determined by an insulator. Critical device limits are dictated by the switching energy and delay and, therefore, the minimum allowable channel length of a MOSFET and the response time of a canonical distributed RC network. Four generic circuit limits are imposed by the static transfer curve of a logic gate, its power-delay product and intrinsic switching delay, as well as the response time of a global interconnect circuit. System limits are the most restrictive bounds of the hierarchy and are based primarily upon chip architecture, the multi-level interconnect network architecture, the power-delay product of the semiconductor technology, the heat removal capacity of the package or the energy capacity of the battery, the clock cycle time and the overall physical size of a chip.
9:00 AM	Invited	EM-WeM-3 Interconnections for Devices and Circuits and Packages of the 21st Century Challenges in Materials, Processing, and Characterization S. Murarka (Rensselaer Polytechnic Institute) The projections of continued shrinking of the semiconductor devices indicate a minimum feature size of 100 nm in 2007 and ~30 nm by year 2015. Also, new devices where material dimensions are as low as 1 to 2 nm are being researched. How do we interconnect these devices and circuits and maintain the desired performance, reliability, and cost-advantages. Traditionally RC delay caused by the interconnection and interlayer dielectric combination has been addressed, leading to suggestions of using lower resistivity metal (e.g., Cu instead of Al) and lower dielectric constant polymers. However, at dimensions as low as 30 nm the metal resistance is controlled by the electron scattering from the bounding surfaces because 30 nm is close to the mean free path of electrons in most metals. Thus electronic conduction may be questionable especially for the first level of interconnections that connect devices on semiconductor. This talk will review the issues and present an outlook at the alternatives: eliminating or minimizing R, C, or both, cleverly cooled circuits/packages to liquid nitrogen temperatures, optical or optoelectronic interconnection schemes, and clever-designing of the circuits and interconnection layouts. Each alternative will require new materials and processes that have to be proven reliable and cost-effective. The present state of the research for the use of Cu or Cu-alloy, high Tc-superconductors, low dielectric constant polymers and aerogels (or xerogels), new vapor deposition, planarization, and etching methods, and evolving characterization technologies will be reviewed.
9:40 AM	Invited	EM-WeM-5 Fabrication in the Sub-100nm Regime D. Kern (University of T\um u\bingen, Germany) Technology road maps project that the minimum feature size in silicon technology will pass the 0.1\mu\m level before the year 2010. While this mainly assumes continued scaling of "standard" MOSFET technology, alternative device and circuit concepts based on quantum effects are investigated, in particular approaches involving resonant tunneling, single electron charging effects or a combination of Coulomb interaction and energy quantization in quantum dots. The key task in fabrication remains the generation of small and precise structures, eventually in large numbers. This is true for scaling conventional technology, requiring sub-100nm gates, contacts, isolation trenches, shallow junctions, all aligned with respect to each other to a fraction of their size, or for quantum effects to be explored. In the latter case, in particular, dimensions approaching a few manometers are required for room temperature operation. Typical fabrication processes involve growth of specifically tailored materials using MBE or CVD type processes for dimensional control in vertical direction, combined with a wide range of lithography and pattern transfer techniques for control in lateral directions. The available options ranging from optical lithography to SXM techniques, together with their limitations, will be discussed, primarily in terms of resolution, accuracy and throughput. Self-assembly techniques with macromolecules or clusters of material separated by appropriate spacer molecules, combined with novel device concepts utilizing such materials and the combination of these techniques with conventional patterning may lead to efficient fabrication routes in the sub-100nm regime.
10:20 AM	Invited	EM-WeM-7 Technology Challenges: A Silicon Device and Integration Perspective S. Tiwari (IBM T.J. Watson Research Center) In the midst of dooms-day predictions and effervescent advocacy of fundamentally new solutions, the silicon world has kept growing and adapting as one of the more creative and helpful inventions of industrial age. The move from building blocks of bipolar to CMOS transistor structures; the changes in technology from metal gates to poly-silicon, silicon dioxide to nitrided oxides, diffusion and/or epitaxy to implantation, metal contacts to silicided contacts, iso-thermal annealing to rapid-thermal annealing, lowering of operating voltages, etc., have all taken place as economic and engineering responses to applications demanding higher integration densities at lower power and higher speeds. The fundamental limitation on the field-effect transistor, a device where the source and drain reservoirs are separated by a channel that can be raised or lowered in energy, is only that of charge leakage in the channel (Thomas-Fermi screening length of greater than 2 nm for degenerate conditions) and the size of electron wave packet/wavelength (approximately 2 nm). Limits of economics are more severe than limits of physics. As in the past, technology must find economic solutions to improvement and control of devices as they shrink. Improvement and control of dopant profiles, contact metallurgies, parasitic resistances, scaling of lengths and spacers, morphologies, insulators and dielectrics, interfaces, etc., are clearly needed in order to control the characteristics of devices. Modeling, likewise, must aid in finding economic solutions through rigorous foundations which allow a predictive capability rather than computer-aided speculation. In this talk, I will take examples from current state-of-art, the path to it, and their relationship to the needs of circuits and applications in order to discuss the problems and possible directions of research for the future.
11:00 AM	Invited	EM-WeM-9 Toward Giga-scale Si Integrated Circuits A. Ourmazd (Institute for Semiconductor Physics, Germany) The dramatic improvements in Si technology, sustained for over thirty years, are now expected to produce commercially viable circuits with a billion elements or more, within a decade. To the customer, these changes appear as exponential increases in the number of circuit elements per chip, exponential reductions in the price per element, and less rapid, but important improvements in speed and power characteristics. To the technologist, these advances have stemmed from exponential reductions in minimum feature size and defect density, and less rapid, but significant increases in device complexity and die size. This talk has the following aims: (a) Outline the important trends in integration of Si circuits; (b) Describe the key elements needed to sustain these trends; (c) Present early results obtained from very small Si devices and circuits; (d) Explore the fundamental limits that may ultimately force traditional integration trends to saturate.