ALD/ALE 2021 Session AA4: Applications in ULSI FEOL: High-k

Etch stop layers (ESL) are commonly used to protect critical films. This is also the case for 300 mm 2D material integration where HfO₂ ESL is used first for the contact trench etch, and again for the damascene high-k first/top gate last process steps. For the latter, the HfO₂ ESL also serves as top gate dielectric and is hence highly sensitive to plasma-induced damage (PID).

In this paper, two main approaches were investigated for the SiO₂ removal stopping on HfO₂. Conventional, Continuous-Wave (CW) plasma experiments (Fluorine-based) were performed in the ICP, and the Quasi-Atomic Layer Etch (Q-ALE) in CCP reactor, both from Lam Research Corporation. The goal was to explore Q-ALE and make a general comparison between the two approaches. The advantage of ALE, as well as Q-ALE over CW plasma etch is its unique capability to remove the material with an angstrom precision, causing minimal or no damage and material removal with high etch selectivity.

Simple metal oxide metal capacitor (MIMCAP) test vehicle was used for the study. First, a 10nm TiN bottom electrode was deposited on Silicon wafers, followed by a 10nm HfO₂ layer and a SiO₂ hard mask. The SiO₂ is etched with a spin-on carbon/spin-on glass/photoresist stack, stopping on the underlying HfO₂. Following the plasma processing, the TiN/W top electrode metal stack is deposited in the trenches, and planarized with chemical mechanical polishing (CMP) to electrically isolate the devices.

Our results show that for the CW approach, longer over-etch (OE) thins the HfO₂, and consequently, increases the leakage current and lowers the breakdown voltage. In the case of Q-ALE, the HfO₂ thickness is intact even with the prolonged OE, implying high process selectivity to HfO₂, with no morphological or electrical evidence of PID. However, in the case of Q-ALE, longer OE causes more spread in the electrical performance. This is likely the result of more residues, formed during the passivation step, and remaining on the HfO₂ surface after processing. (Further process performance improvement can be potentially achieved using the effective post-plasma cleaning, but it was not the goal of this study).

We conclude that Q-ALE is a promising technique for the applications where the HfO₂ ESL also serves as the gate oxide. The high etch selectivity and low PID make it ideal for novel integration flows, like 300 mm 2D material integration.

The formation of self-aligned MOSFET gate stacks via area-selective atomic layer deposition (AS-ALD) of high-κ dielectric and metal films offers a route to reduce the number of lithography steps, maintain a low thermal budget, and improve performance by eliminating overlap capacitance. In this work, a new method for bottom-up masking of semiconductor surfaces and nano/microstructures is combined with AS-ALD to fabricate a high-performance gate stack that is self-aligned to the underlying doped source-drain regions. We begin with the SCALES process, which involves a poly(methyl methacrylate) (PMMA) brush grown from a silicon surface [1]. The PMMA brush is then patterned via a mild selective etching of the underlying semiconductor based on the Si dopant concentration. KOH etches lightly doped Si much faster than heavily doped Si, allowing for selective removal from only the lightly doped regions. The full gate stack is then deposited via AS-ALD in areas where the brush has been removed, as shown in Figure 1. Figure 2 shows XPS data of an example gate stack sequence deposited via AS-ALD, including a HfO₂ dielectric and a Pt gate electrode. Both spectra show good selectivity of deposition toward the regions where PMMA had been removed. Figure 3 shows the C-V characteristics of a gate stack on both a silicon substrate that did not undergo the PMMA process as well as a silicon substrate in which the PMMA was removed via etching. The C-V characteristics are almost identical for both cases indicating that the PMMA brush growth and removal does not strongly impact the silicon-HfO₂ interface. The maximum capacitance was used to determine a relative dielectric constant of ~24 which is expected for HfO₂. The interface state density was extracted from the C-V characteristics to be on the order of 10¹² cm^-2. Ongoing work aims to reduce defect density in this and other high-κ dielectrics (e.g. TiO₂, Al₂O₃, ZrO₂).

[1] Mohabir, Amar T., et al. "Bottom-Up Masking of Si/Ge Surfaces and Nanowire Heterostructures via Surface-Initiated Polymerization and Selective Etching." ACS nano 14.1 (2020): 282-288.