Heterogeneous integration of multiple types of Integrated circuit chips on a single package is an emerging area in advanced packaging that has made significant impact to High Performance Computing (HPC) devices. In this presentation, we will discuss the evolution of heterogeneous System in Package (SIP) packaging technologies. We will provide an overview of key drivers and metrics for enabling advanced die to die and on package interconnect technologies . We will cover the areas of innovation needed in materials, equipment, process and design in advancing the next generation of heterogeneous SIP packaging technologies. Finally, we will cover some of the unique requirements needed of basic thin film materials used in electronics, as it applies to packaging.

Aluminium scandium nitride (AlScN) has emerged as a promising material for fabrication of bulk acoustic wave (BAW) and surface acoustic wave (SAW) devices by virtue of its high piezoelectric properties and improved electromechanical coupling. Despite the high interest, AlScN remains relatively unexplored material in terms of the structural properties and device applications. We recently demonstrated that non-polar Al_0.77Sc_0.23N offers a pathway for further improvement in electromechanical coupling for SAW resonators by aligning the acoustic wave along the c-axis direction with the largest piezoelectric response[1]. The metastable nature of Al_1-xSc_xN at higher scandium concentrations, that causes formation of abnormally oriented grains (AOG) protruding from surface of the films, has been a challenge for its adoption for SAW applications. We succeeded in achieving the growth of completely AOG-free non-polar in-plane oriented Al_1−xSc_xN films with even higher Sc content of x=0.3 by reactive magnetron sputter epitaxy. Various sputtering process conditions were investigated focusing on the Al_0.7Sc_0.3N(11-20)/Al₂O₃(1-102) film. Surface quality and films with RMS roughness less than 0.5 nm could be obtained. The atomic force microscopy (AFM) and x-ray diffraction (XRD) studies of films show a unique striated grain morphology along the c-axis of the film revealing in-plane anisotropy. While the XRD measurements confirm the in-plane orientation of Al_0.7Sc_0.3N(11-20), the φ scans also reveal a distorted wurzitic structure and structural anisotropy. The structural anisotropy is studied by combining transmission electron microscopy, high resolution XRD and AFM. Furthermore, the optimized Al_0.7Sc_0.3N(11-20) films were used to fabricate SAW resonator test structures. Different in-plane SAW propagation directions were used to map the angular distribution of effective electromechanical coupling as well as piezoelectric properties of non-polar AlScN thin films and correlated to the results of structural anisotropy study.

[1] A.Ding, et al., APL 116(10), 101903 (2020).

The semiconductor industry is advancing from a SoC (system on ship) approach towards developing various integration schemes involving SiP (system in package) to meet the future requirements of performance and cost. This is commonly referred to as heterogeneous integration and is being utilized for 2.5D/3D chip stacking, high density fanout and chiplets. All these approaches rely on the use of metallic interconnects including TSVs (through-silicon vias), micropillars, fine line RDL, and hybrid bonding.

In the case of 3D stacking with TSVs for memory, we see an increase in the number of stacking layers and reduction of critical dimensions to accommodate higher I/O counts. The interconnects in high density fanout comprise of fine line RDL and megapillars. To meet the performance requirements line dimensions are shrinking from 5x5µm to sub 2x2µm L/S, along with incorporation of a multilayer approach. Megapillars typically range from 100 to 200µm CD with varying aspect ratios depending on the integration scheme and performance needs. Copper pillars with sub-40µm pitch are referred to as micropillars which will eventually need to be replaced by hybrid bonding as the dimensions shrink below 10µm.

Scaling requirements for each of these interconnects pose challenges that need to be addressed by making process, materials, and integration changes. In the case of TSVs, higher aspect ratios necessitate the need for alternate metallization schemes. For micropillars, increase in bump density results in challenges to assembly yield and reliability, while for fine line RDLs stress induced damage and topography control needs to be solved. Finally, in the case of hybrid bonding the key requirement of lower thermal budget for yield improvement needs to be addressed for die-to-wafer and wafer-to-wafer stacking.

This presentation will cover how select deposition processes and material changes provide solutions to the scaling challenges posed by interconnects utilized in various heterogenous integration schemes.