Metal-insulator-metal (MIM) structures with transition metal oxide (TMO) are typically used to implement resistance random access memory (RRAM) device. The specific structures in this paper are TiN/WO_x/Pt and TiN/WSiO_x/Pt. A constant voltage forming method is used to induce repeatable bipolar resistance switching behavior. Comparing with the TiN/WO_x/Pt structure, the TiN/WSiO_x/Pt device exhibits excellent characteristic with good endurance of more than 10⁵ times, long retention time of 10⁴ s in 125℃ and more stable in resistance switching state. Furthermore, the switching mechanism is investigated by current-voltage (IV) curve fitting and material analysis. From the experiment result, the conductive path of the TiN/WO_x/Pt RRAM device is disorder due to its filament formed everywhere in the switching layer. In addition, the switching behavior in the TiN/WSiO_x/Pt device is regard as point electric filed by localizing filament between the interface of top electrode and insulator. The TiN/WSiO_x/Pt device presents a highly stable and excellent memory feature for developing next generation nonvolatile memories.

Thermal annealing effects and mechanism studies on the resistive switching characteristics of a thin FeO_x-transition layer were demonstrated by a TiN/SiO₂/FeO_x/Fe structure, including bipolar switching behaviors, statistics of set and reset electrical characteristics, and retention. Increase of the thermal budget on the structure shrinks both the operation voltage and variation as well as improves the device operation stability and power dissipation. Cross-section image, crystallinity and composition analyses of the transition layer were examined by tunneling electron microscope, X-ray diffraction and X-ray photon-emission spectra depth profiles, respectively. In addition, the FeO_x-contained structure switching mechanism was also studied by statistics of the electrical parameter results. Retention property at room temperature and 85^oC keeps both resistance states over 6×10⁴ sec, providing the potential for nonvolatile memory applications.

Imprint lithography has drawn a lot of attention as one of the promising technologies for the transfer of nano/micro-patterns due to its simplicity, low cost and high throughput. Complex-shaped structures such as micro-channels, micro-trenches and non-flat patterns over large areas are commonly required for semiconductor industry. Electroless nickel (EN) plating process is much simpler than e-beam, X-ray lithography, and UV photolithography. The aims of this study are to evaluate the feasibility for the replication of micro-patterns by EN plating method and to examine the effect of additives on the surface morphology by scanning electron microscopy (SEM) and microhardness by nanoindentation. The micro-pattern with line-width 400 nm and pitch 800 nm on silicon substrate ( 24 mm x 24 mm ) can be coated uniformly by EN plating. A blind hole structure of 200 nm in diameter and 300 nm in depth with SiO₂ sidewall of 400nm in thickness on 100 mm x 100 mm silicon substrate could be filled with EN. After removal of SiO₂ and silicon by 30% KOH aqueous solution, the imprinted columnar array of EN is clearly shown by SEM. Additions of saccharin and SDS wetting agent to EN plating solution are closely related to the smoothness of imprinted surface, but only slightly increases the microhardness of the coating from 6.303 GPa to 6.437 GPa with 15mN loading. Post-treatment of stress relaxation after EN plating is necessary to minimize potential hydrogen embrittlement adverse effect. Excellent pore-filling capability and step coverage of EN plating have been shown during micro-imprint.

Metal silicides have been widely used in ultralarge scale integrated (ULSI) circuits to reduce the contact resistance of source/drain (S/D) in complementary metal-oxide-semiconductor (CMOS) devices. Currently, the most commonly used silicides are TiSi₂ and CoSi₂. The TiSi₂, the transformation from the high resistivity C49 phase to the low resistivity C54 phase is nucleation limited, causing linewidth dependence of the sheet resistance for gate lines narrower than submicrometer dimension. Therefore, CoSi₂ and NiSi have emerged as the most promising candidates to replace C54-TiSi₂ phase in Self-Aligned Silicide (Salicide) technology.

Nickel mono-silicide (NiSi) with low sheet resistance (Rs), line-width independence and relatively low silicon consumption has received much attention in recent years. The main disadvantage of NiSi is low thermal stability. The formation of NiSi takes place around 350^oC, and the phase transition of NiSi to the high resistivity NiSi₂ phase occurs at over 700^oC, which limits its application. Nickel silicide agglomeration easily occurs at a temperature above 600^oC, and the related phase transformation NiSi₂ degrades device performance and gives rise to some reliability issues.

In this study, the effects of nickel nitride (NiN_x) capping layers on the formation of nickel silicide have been investigated. Using the NiN_x replace the capping layer (TiNx) with the anticipation that the resulting materials would be suitable for next-generation CMOS processes. Nickel silicide films using NiN_x (N ratio flow of 0~30 sccm) are used in an RTA process. They exhibit advanced thermal stability at 300-800^oC/30s, and inhibit surface agglomeration better than the TiN_x and non-capping layer nickel silicide. The diffraction peaks of the NiN_x films deposited with N₂ flow ratios rang from 10~20 sccm has a Ni₄N peak, when N₂ flow ratios rang from 25~30 sccm has a Ni₃N peak. The Ni₄N phase is inhibit surface roughness and thermal stability properties better than Ni₃N phase. The results of the Ni₄N remove rate faster than Ni₃N and NiSi and the thermal stability and inhibit surface agglomeration behavior still Ni₄N has better than Ni₃N on the nickel silicide. Final, the Tafel corrosion rate curves of the NiN_x (Ni₄N and Ni₃N) and nickel thin films in the H₂SO₄:H₂O₂=4:1 were investigated.

Conventional Co alloy based recording media are unable to fulfill the requirement of high density magnetic recording up to 1 Tbit/ in² due to phenomenon like superparamagnetism. L1₀ CoPt is a potential candidate due to its large K_u value of 10⁷ ergs/cm³. The high K_u value of CoPt allows smaller and thermally stable grains (of size 3nm) against superparamagnetism[1]. Such small grain size is able to increase the areal density beyond 1 Tbit/ in². However, as deposited CoPt film shows fcc phase. To achieve the desired phase, high deposition temperature or postdeposition annealing at temperature higher than 600°C is required [2-4]. High deposition temperature increases the grain size which effectively reduces the signal-to-noise ratio. L1₀ CoPt–SiO₂ nanocomposite provides control the CoPt grain size and intergranular magnetic interaction [5]. However, the effects of SiO₂ addition on chemical ordering and magnetic properties of Co/Pt multilayers will be interesting to probe.

In this study we have prepared different set of thin films containing different number of multilayers of Co and Pt with SiO₂ as a buffer and capping layer on Si (100) substrates. Deposition were made in a custom built DC/RF sputtering chamber by varying number of multilayers of SiO₂ /Co/Pt/SiO₂. In each set of thin films thichkness of various layers were kept fixed while the number of multilayers were varied. Samples were annealded up to (400^oC -700^oC) in Ar atmosphere. Structural studies of these films were done by X-ray diffraction and Field Emission Scanning Electron Microscopy, Atomic Force Microscopy and Transmission Electron Microscopy while magnetic measurements were done by SQUID (Superconducting Quantum Interference Device) magnetometer. Structural properties of as deposited thin films show the formation of fcc phase of CoPt nanoparticles while annealing at higher temperatue shows the change in the crystal structure. Magnetic Measurements show the high value of coercivity for both longitudinal as well as in perpendicular direction.

1. R. Sbiaa and S. N. Piramanayagam, Recent Patents on Nanotechnology 1, 29 (2007).

2. Y. Xu, Z. G. Sun, Y. Qiang, and D. J. Sellmyer, J. Magn. Magn. Mater. 266, 164 (2003).

3 O. Kitakami, Y. Shimada, K. Oikawa, H. Daimon, and K. Fukamichi, Appl. Phys. Lett. 78, 1104 (2000).

4. C. Chen, O. Kitakami, S. Okamoto, and Y. Shimada, Appl. Phys. Lett. 76, 3218 (2000).

5. C. Chen, O. Kitakami, S. Okamoto, and Y. Shimada, IEEE Trans. Magn. 35, 3466 (1999).