Materials and Processes for Advanced Interconnects and Low k Dielectrics

Wednesday, May 2, 2001 2:10 PM in Room Sunrise

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2:10 PM H1-2-3 New Concepts in Formulating Diffusion Barriers/Adhesion Promoters for the Interconnect Technology of Tomorrow
S.P. Murarka (Rensselaer Polytechnic Institute)
As we move into the 100 nm regime of the minimum feature size device technologies, a need of (a) a new diffusion barrier/adhesion promoter (DBAP) material compatible with Cu metallization and processes or (b) a new concept that may lead to the elimination of the DBAP material is becoming obvious. The need arises due to a lack of DBAP materials with electrical resistivities comparable to that of Cu. Presently used DBAP materials have resistivities in the range of 100 - 300 micro-ohm cm and are effective when used in thicknesses greater than 10 nm causing a serious increase in the total interconnect resistance. DBAP materials must also be compatible with the inter layer dielectric material that may change from silicon dioxide to a low dielectric constant material in near future. A similar need of the DBAP may arise for newer interconnect concepts (eg. optoelectronic), where a new class of materials have to be compatible with the silicon based device/circuits. This presentation will briefly review the present status and the future of Cu interconnect technology. This will be followed by a discussion of the need, existing materials and their limitations, and the new emerging concepts that are being explored to satisfy the DBAP materials’ requirements.
2:50 PM H1-2-5 Integration Schemes of HDP-FSG for 0.18 µm Logic Process
Y.L. Cheng, M.S. Feng, W. Junwu (National Chiao Tung University, Taiwan, ROC); Y.L. Wang (Taiwan Semiconductor Manufacturing Company Ltd., Taiwan, ROC); J.K. Wang (Taiwan Semiconductor Manufacturing Company, Taiwan, ROC)
The full-flow HDP-FSG integration scheme, namely, the Si-Rich liner/FSG/FSG CMP/Post CMP treatment/Cap oxide scheme was investigated. The HDP-SRO is considered to be a suitable candidate for application as liner and cap oxide layer not only because it can block the F diffuse out after the FSG was annealed ( 3 hours at 400C in N2 ambient ) but also because it can prevent the FSG from the moisture attack after the FSG was conducted to the PCT test ( 6hours at 2 atm and 120C). Numerous post-CMP treatments wee evaluated to reduce the H content at the FSG interface. By a sreious SIMs analysis, the HDP-N2 treatment was demonstrated to be the most effective way to reduce the H content at the FSG interface, though there was a little F lost found. Moreover, the TDS spectra also showed that the HDP-N2 treated FSG film revealed the highest HF outgassing temperature ( -430C ). After implememt this scheme on pattern wafer by thermal cycle test, HDP-FSG films with F concentration up to 5% ( Peak-high ratio by FTIR) can be integrated successfully with this full-flow approach. @footnote@M. J. Shapiro, et al., CVD of Fluorosilicate Glass for ULSI Applications. Thin Solid Films, 1995. 270: p. 503-507. T. Homma, Fluorinated Interlayer Dielectric Films in ULSI Multilevel Interconnections. Journal of Non-Crystalline Solids, 1995. 187: p. 49-59. S. Lee and J.-W. Park, Effect of Fluroine on Dielectric Properties of SiOF Films. Journal of Applied Physics, 1996. 80(9): p. 5260-5263. M. K. Bhan, J. Huang, and D. Cheung, Deposition of Stable, Low K and High Depostion rate SiF4-Dope TEOS Fluorinated Silicon Dioxide (SiOF) Films. Thin Solid Films, 1997. 308-309: p. 507-511.
3:10 PM H1-2-6 Filtered Cathodic Vacuum Arc Deposition of Thin Film Copper
S.P. Lau, J.R. Shi, Y.H. Cheng, B.K. Tay (Nanyang Technological University, Singapore); X. Shi (Nanofilm Technologies International, Singapore)
A major obstacle for metallization application of filtered cathodic vacuum arc (FCVA) is the presence of microparticles. By using an off-plane double bend magnetic filter, metallic films can be deposited with relevant deposition rates and free of microparticles. Copper has drawn much attention as a new interconnection material for deep submicron integrated circuits as a replacement for Al. FCVA technique is not only able to deposit fully conformal diffusion barriers of Ta and TaN but also Cu layer. Copper thin films with low electrical resistivity were deposited by FCVA technique at room temperature. The structure of the films was determined by X-ray diffraction, transmission electron microscopy and atomic force microscopy. All the copper films have a polycrystalline structure, and the grain size increases with increasing film thickness. It was found that there is a critical film thickness about 135 nm, above which the resistivity has an almost unchanged value of 1.8 µ@ohm@ cm. Below the critical thickness, the resistivity increases with decreasing thickness. The influence of substrate bias on the structure, surface morphology, internal stress and resistivity are also studied.
3:30 PM H1-2-7 Integration of MOCVD Titanium Nitride with Collimated Titanium and Ion Metal Plasma Titanium for 0.18 µmm Logic Process
J.K. Lan (Chiao-Tung University, Taiwan, ROC); Y.L. Wang (Taiwan Semiconductor Manufacturing Company Ltd., R.O.C.); C.G. Chau (Chiao-Tung University, Taiwan, ROC); Y.L. Wu (National Chi-Nan University, Tawian, ROC); T.C. Wang (Chiao-Tung University, Taiwan, ROC); H.C. Liou (Dow Corning, USA.)
Titanium (Ti) and titanium nitride (TiN) have commonly been used as the barrier and adhesion promoter layer for aluminum and tungsten plug process in VLSI @footnote 1,2,3@. Ti and TiN films have traditionally been processed by physical vapor deposition (PVD)@footnote 1,2@. But when circuit dimensions continue to shrink , the high aspect ratio of metal schemes limit the PVD Ti and TiN applications @footnote 4@. For titanium nitride , the chemical vapor deposition (CVD) @footnote 4,5@ process can meet the aspect ratio requirement. But for titanium , it is difficult to deposit pure titanium metal since titanium has great affinity for oxidation by oxygen and nitrogen @footnote 6@. Collimated and ion metal plasma (IMP) process @footnote 7,8@ are the common approaches for barrier metal deposition beyond 0.18µmm process. The performance of chemical vapor deposition (CVD) titanium nitride had been widely discussed @footnote 9@. The in-situ plasma treatment was found to stabilized the CVD TiN film @footnote 10@. Lower CVD TiN deposition temperature had been found to increase step coverage @footnote 10@. Besides this, lower CVD TiN deposition temperature had also been found to lead to higher film resistivity @footnote 10@. But it is the first time showing that lower CVD TiN deposition temperature (420 @super o@C) can give better contact electric performance for 0.18µmm process. The CVD TiN films in this study are thermally deposited on heated wafers from tetrakisdimethylamino titanium (TDMAT). For IMP titanium(~200Å) process, the experimental data show that the lower CVD TiN deposition temperature (420 @super o@C) gives about 10% to 25% drop on contact resistivity. For collimated titanium(~300Å) process , it shows about 3% to 8% drop on contact resistivity. The lower CVD TiN deposition temperature (420 @super o@C) does not impact the yields. The difference in the integration with collimated and IMP titanium will be presented in this study. The discussion will be presented on the various considerations in support of lower temperature for 0.18 µmm barrier deposition.}
3:50 PM H1-2-8 Interconnect Degredation
F.A Malik (EMMAY Associates/FAST Institute, Pakistan); M Hassan (EMMAY Associates, Pakistan)
Interconnects and associated photo lithography play a dominant role in the feature shrinkage of electronic devices. Most interconnects are fabricated by use of thin film processing techniques. Chemical Mechanical Planarization (CMP) is being widely used for planarization of dielectric as well as metal removal. Both Aluminum (AL) and copper (CU) metalization is deposited. Degredation of interconnects has been observed. Pitting has been seen in oxide as well as metal lines in multilevel metalization. Mouse bites have been encountered in Aluminum while missing lines have been seen in copper. Interconnect degredation is a serious reliability concern in high performance devices. Certain preventive mechanisms have been evaluated with some success.
4:10 PM H1-2-9 Thermomechanical Properteis of a-Si:H and a-Ge:H
M.M. Lima Jr. (UNICAMP-USA, Brazil); F.C. Marques (Instituto de Fisica, Unicamp, Brazil)
Recently, there has been an increasing interest on the influence of the deposition parameters on the mechanical properties of materials used in the microelectronic industry. Parameters such as stress, elastic modulus and coefficient of thermal expansion,CTE, have been studied more often since they are important for the development of stable devices. In the particular case of amorphous semiconductors, there is little information about these properties and more research is still necessary to explain some phenomena that take place in these materials. In this work, the coefficient of thermal expansion and the biaxial modulus of amorphous hydrogenated silicon (a-Si:H) and germanium (a-Ge:H), determined by the thermally induced bending technique, were investigated as a function the network strain and coordination number. The network strain, in terms of the macroscopic stress, depends on the deposition technique and preparation condition, while the coordination number depends on the hydrogen content. We observe that the coefficient of thermal expansion of a-Si:H and a-Ge:H depends on the network strain. For high quality films, which are compressive, the CTE is higher than that of their crystalline counterparts. The structural changing from the crystalline to the amorphous phase and the changing on the coordination number appear to interfere little in the magnitude of the expansion coefficient. On the other hand, the elastic modulus depends on the coordination number following the model proposed by Philips. @paragraph@This work was supported by Brazilian agencies FAPESP and CNPq.