Materials and Processes for Advanced Interconnects and Low k Dielectrics
Wednesday, May 2, 2001 8:30 AM in Room Sunrise
H1-1-1 Ultra Low k Mesoporous Silica Dielectrics
S. Baskaran (Pacific Northwest Laboratory); J. Liu, Xiahong Li, C. Coyle, J. Birnbaum, G. Fryxell, G. Dunham, R. Williford (Pacific Northwest National Laboratory); S. Jin (SEMATECH)
The semiconductor industry is currently targeting new intermetal dielectric films with k < 2.5 for advanced interconnects, and it is anticipated that as the packing density of metal lines on the semiconductors continues to increase, intermetal dielectric films with k < 2.0 will be soon required. Highly porous silica films with pore sizes in the nanometer scale are potentially useful as intermetal dielectrics with k in the range of 1.5 to 2.2. In this presentation, we discuss molecularly templated synthesis, pore structure and properties of mesoporous silica films. This synthesis approach allows rational control of the porosity, pore size (to less than 5 nm) and shape. Deposition of mesoporous films has been demonstrated on large wafers. Copper single-damascene one-level test structures have been built using mesoporous silica as the intermetal dielectric. No major structural failures have been observed after chemical mechanical planarization on both blanket films and patterned wafers, indicating relatively good mechanical integrity for a highly porous structure. With controlled film synthesis and dehydroxylation conditions, mesoporous silica films with k @super email@example.com and elastic modulus of 4.0 GPa have been synthesized at PNNL. A key practical challenge is synthesis of films with high mechanical integrity, and k values that are essentially invariant after exposure to moisture, while adhering to temperature/time/environment process constraints in building mult-level copper interconnects. Further developmental work required to address potential performance limitations and integration challenges with open-pore structures will be briefly discussed.
H1-1-3 Porous Materiasl as Low-k Dielectrics for Electronic and Optical Interconnects
J.L. Plawsky, A. Jain, S. Ponoth, S. Rogojevic, N. Agarwal, W.N. Gill, P. Persans (Rensselaer Polytechnic Institute)
The need to decrease signal delay and crosstalk in interconnects within integrated circuits is becoming increasingly important as device dimensions shrink. Electrical connections require lower resistivity metals and lower dielectric constant insulating films to meet future goals. Even those materials may not provide for sufficient signal bandwidth and so optical interconnections are also envisioned. Porous materials offer the opportunity to make scaleable dielectric constant materials for both electrical and optical interconnections. At Rensselaer we have been working on projects using porous silicate materials as low-k dielectrics and low refractive index "cladding" materials. This talk will focus on several issues associated with these materials focusing on the relationship between the porosity of the material and its optical, electrical, interfacial, mechanical, and thermal properties. We find porosity has profound effects on the adhesion and stability of thin metal or dielectric films deposited on porous materials. In some instances such as copper, porosity actually enhances the adhesion and stability of the film. In others such as silicon nitride or tantalum, small changes in porosity lead to buckling or delamination of the film. The interfacial properties also affect diffusion of metals into these films. Thus diffusion of copper into silica xerogel films is an order of magnitude or more less than that through solid SiO@sub 2@. This may be the result of surface passivation processes used to make the materials hydrophobic. Thermal conductivity and mechanical strength vary exponentially with porosity, a fact that may be correlated to a decrease in solid contact area within the material. Finally, the optical properties of waveguides formed using porous silicate claddings will be discussed. Core/cladding refractive index differences of 0.6 or more are possible making for compact optical waveguide interconnects. Low refractive index, space filling porous materials may also find uses in photonic crystal applications.
H1-1-5 Detection of Reactive Ion Etch Damage in Low k Dielectrics Using Electric Force Microscopy
T.S. Gross, K.G. Soucy (University of New Hampshire); E. Andideh (Intel Corportion)
We will show how electric force microscopy can be used to detect dielectric constant variations caused by reactive ion etching of low k dielectrics with tens of nanometer resolution. Samples of blanket dielectrics were patterned and subjected to reactive ion etching, ashing to remove photoresist, and subsequently backfilled with another dielectric that was not exposed to the ash or reactive ion etch step. Structures were patterned in PTEOS backfilled with PTEOS, PTEOS backfilled with a carbon-doped low k, and a low k backfilled with a low k. These samples were sectioned and polished in cross section and feather section. These sections were interrogated by electric force microscopy that revealed significant damage to the patterned low k dielectric subjected to the etch/ash steps.
H1-1-6 Enhancing the Resistance of Low k Hydrogen Silsesquioxane (HSQ) to Wet Stripper Damage
T.C. Chang (National Sun Yat-Sen University, Taiwan, ROC); Y.S. Mor, C.H. Li, C.F. Tang, S.M. Sze (National Chiao Tung University, Taiwan, ROC); P.T. Liu, Y.L. Yang (National Nano Device Laboratory, Taiwan, ROC); J.K. Lee, F.Y. Shih, Eric Tsai, Grace Chen (Dow Corning Taiwan Inc., Taiwan, ROC)
The interaction between low-k hydrogen silsesquioxane (HSQ) film and wet stripper was investigated in this work. Owing to stripper are always used to remove photoresister in widespread and that is an unavoidable step in IC integration process. However, the stripper with high alkalinity leads to the hydrolysis of HSQ film, and results in the formation of Si-OH bonds in HSQ. This is consistent with FTIR spectra. Si-OH bonds in HSQ film can react with moisture easily. This will lead to the increase of dielectric constant and leakage current of HSQ film. Therefore, significant dielectric degradation occurs after photoresist stripping. By applying H@sub2@ plasma pre-treatment to the HSQ film, the leakage current is decreased significantly and the dielectric constant can be maintained a low value. H@sub2@ plasma treatment can passivate the HSQ surface and prevents either the formation of Si-OH bonds and moisture uptake in the HSQ film. Dielectric degradation due to photoresist stripping process is thereby avoided by H@sub2@ plasma treatment. These experiment results indicate that H@sub2@ plasma treatment is a promising technique for integrating the HSQ as intermetal dielectric application.
H1-1-7 Porous Dielectrics for On-Chip Applications
R.D. Miller (IBM Almaden Research Center)
The unrelenting increase in device densities in advanced semiconductor chips presents a number of serious challenges for the wiring interconnects. The recent switch from aluminum to copper metallurgy provides temporary relief from the increasing signal delays caused by the continual device scaling. Equally important, however, is the dielectric constant of the interconnect insulators which needs to be driven lower while maintaining the mechanical, electrical and thermal properties necessary for integration and operation. A particular challenge is presented for the generation and utilization of ultra low-k materials (k<2.0) which will require porous materials.I will discuss the generation of nanoporous organosilicates using sacrificial, thermally labile macromolecular pore generators to produce nanoporosity in thin films for dielectric applications.
H1-1-9 From Tribolotical Coatings to Low-k Dielectrics for ULSO Interconnects
A. Grill (T.J. Watson Research Center)
The quest for improving the high performance in ULSI circuits is driving the search for new materials with low dielectric constants (k < 3.0) for the back-end-of-the-line (BEOL) interconnect structures. In parallel to the investigation of novel materials, there is a competition between the methods of preparation of their thin films for the integration in the ULSI chips, the two main techniques being spin-on deposition and plasma enhanced chemical vapor deposition (PECVD).@paragraph@ It has been found that, by adjusting the PECVD deposition conditions of hydrogenated diamondlike carbon, typically prepared as a wear and corrosion resistant coating, its dielectric constant can be reduced to values ranging from 3.3 to 2.7. Incorporation of F in the DLC further reduced the dielectric constants to values as low as 2.4. While these are attractive values, the integration of the materials in the ULSI chips imposes a significant number of requirements, which are not easily achieved by the new dielectrics. The integration of DLC has been demonstrated up to two levels in a Cu based damascene structure, however FDLC could not be integrated by processing at the temperature of 400@super o@C typically used in the BEOL processing.@paragraph@ For improving the integrability and reliability of the low-k material a hybrid composition of DLC and SiO@sub 2@ has been developed. Carbon doped oxides, or SiCOH films, comprising Si, C, O and H, deposited by PECVD deposition technique have achieved dielectric constant values as low as 2.8. The dielectric constant of such materials can be further lowered by enhancing the atomic level porosity in the films. This nanoporosity enhancement can be achieved by depositing multiphase films, containing at least one thermally unstable phase, and annealing the films to remove this labile phase from the material. Dual phase materials have been prepared by PECVD from mixtures of SiCOH precursors with hydrocarbons. Depending on the deposition conditions, choice of the hydrocarbon, and its concentration in the feed gas, the dielectric constant of the stabilized films reached values significantly lower than previously reported. @paragraph@ The talk will discuss the preparation of the low-k materials, their characterization, integration issues, and approaches for enabling the integration of the low-k films in the interconnect structures of the ULSI chips.
H1-1-11 Characterization and Reliability of Low Dielectric Constant Fluorosilicate Glass and Silicon Rich Oxide Process for Sub-0.15 Micron Device Application
Y.L. Wang (Taiwan Semiconductor Manufacturing Company Ltd., Taiwan, ROC)
Several integration issues, such as Fluorine (F) distribution, F thermal stability, gap fill capability, capacitance reduction, and via resistance of Fluorosilicate Glass (FSG) prepared by Chemical Vapor Deposition (CVD) method were investigated for 0.18 m devices. In this study, FSG-CVD films show different F concentrations at different locations on 8â€ wafer. In addition, FSG film shows poor thermal stability and F diffuses out of the film after high temperature annealing and pressure cook test (PCT). However, the thermal stability of FSG film can be improved by capping an oxide layer. The results indicate that Silicon Rich Oxide (SRO) has better effect to block the F diffusion out of FSG films at high temperature than Plasma Enhanced Oxide (PE-OX). For the gap fill capability, HDP-FSG can fill all 0.23 m gaps and some of 0.21 m gaps with aspect ratio less than 3.8 but not 0.19 m gaps. 6,000A HDP-FSG film with 600A USG liner and 14,000 A cap layer shows approx. 7.5% to 7.7% capacitance reduction on 0.23 m/0.23 m gaps when compared with undoped silicate glass (USG). In addition, FSG has a larger capacitance reduction on the wider metal lines than the thinner metal lines at the same gap size due to capacitance fringe effect. The via resistance for 0.26 micron ochm unlaned via of HDP-FSG film is also similar to that of USG.