With ever increasing device density and shrinking feature dimensions, successful plug and interconnect metallization for 0.25 μm technology and beyond becomes very critical for the semiconductor industry. Utilizing advantages of CVD and PVD aluminum processes, we have successfully applied an integrated metallization scheme, the Cool Al process, to the back-end device fabrication for 0.25 μm technology. This integrated process allows low temperature aluminum metallization (< 360C), and is capable of reliably filling sub 0.25 μm structures.

The CVD aluminum and PVD aluminum deposition processes have been integrated on a Endura cluster metallization tool for the first time. A thin CVD aluminum film is first deposited on a nucleation film, typically Ti or Ti/TiN, using dimethyaluminum (DMAH) as precusor, at a process temperature of ~ 260C. Without vacuum break, a PVD aluminum deposition is carried out to complete the via fill. The contaminant-free, comformal thin CVD aluminum servers as an ideal wetting layer for the PVD aluminum planarization step, allowing enhanced diffusion of aluminum atoms to flow into vias at lower process temperature. In this work, we have used three different integration sequences to process the devices wafers with various nucleation films for CVD aluminum: (1) Coherent Ti; (2) Coherent Ti and CVD TiN; and (3) Coherent Ti, with an thin PVD aluminum film. Sequence (2) eliminates the TiAl₃ formation in the vias, whereas sequence (3) results in better film texture. Excellent electro-migration performances were obtained on these devices, equal to or better than that of standard W technology. In addition, the via resistance for the three sequences will be presented and compared with the W technology. Lastly, the surface morphology and texture for the aluminum film characterized using AMF and SEM will be presented.

In summary, this single-pass aluminum plug and interconnect metallization process provides reliable via fill for 0.25 μm technology at low temperatures, with excellent electrical and reliability results. It also simplifies the manufacturing sequence, compared with other plug-fill technologies, therefore reducing the cost and increasing the overall production throughput.

As dimensions shrink, packing densities rise and vertical integration continues, device manufacturers are seeking metallization solutions that combine low costs with high performance and reliability. In the fields of high performance microprocessors and DRAM's, new interconnect challenges are testing device designers and equipment vendors alike.

In the majority of DRAM's, stacked capacitor structures are used. The continuing drive to reduce cell size without losing storage capacity has increased the complexity and therefore the height of the capacitor structure. Consequently, as memory density rises, so does contact hole aspect ratio. In advanced DRAM manufacture, traditional metallization techniques will have difficulty maintaining yield as aspect ratio's rise above 6:1. Furthermore, the cost and density benefits of dual damascene processing are expected to be exploited by DRAM manufacturers, putting additional demands on the metallization scheme.

At and beyond the 0.25 μm node, interconnect delay replaces gate delay as the limit on microprocessor device performance. In response, 1997 saw a rapid acceleration in the development of low resistance copper interconnect schemes. In parallel, other workers have found significant speed benefits in combining Aluminium interconnect with low capacitance dielectrics. Dual damascene patterning techniques are also the subject of intense development in advanced logic lines.

This paper discusses the Forcefill process. This technology uses high pressure to assist fill of contact holes and vias. The paper will discuss the challenges of Aluminium plug processing and will present data from a novel in-situ process designed to extend hole-fill performance to very high aspect ratio structures. In addition, data will be given demonstrating the effectiveness of the process in dual damascene schemes. Finally, the paper will discuss the relevance of the Forcefill technique to the new materials and demands of the sub-0.25 μm era.