AVS 70 Session AP1+EM+PS+TF-MoA: Area Selective Deposition (ASD) II

K. Tapily, J. Smith, A. deVilliers, G. Leusink

TEL Technology Center, America, LLC, 255 Fuller Road, suite 214, Albany, NY 12203

To achieve higher performance, higher density, and lower cost, for decades the semiconductor industry has relied on aggressive scaling of the device feature size using top-down lithography. Additionally, scaling is driving the need for new materials introduction, new processes and new device architectures increasing the integration complexity. As a result, the industry has introduced several scaling boosters such as high k / metal gate, stress engineering, air gaps and recently area selective deposition to meet the power performance area cost or PPAC requirement.

Advanced device architectures such as gate-all-around (GAA) and complimentary field-effective transistors (CFET) require additional design / technology co-optimized (DTCO) solutions to continue the device scaling roadmap.Selective deposition of materials is fundamental not only for the reduced cost and complexity of manufacturing these advanced devices, but also as fundamental solutions to promote power / performance / CPP scaling of these advanced device architectures.

Surface engineering iskey in successfully realizing defect free area selective deposition. Surface sensitive and reaction driven processes such atomic layer processes (deposition and etch) will be key enabler in some of the required selective deposition processes (1).

This talk will discuss the status and approaches of area selective deposition technology and challenges the industry is facing in implementing future technology nodes. We will go over multiple examples of how novel selective deposition processes can accelerate the industry roadmap in terms of PPAC scaling.

References:

1. G. N Parsons, R. D Clark, Chem. Mater., 32(12), 4920 (2020).

With the constant increase of complexity in integrated systems, more and more connections are required between adjacent chips. Advanced packaging technologies using heterogeneous integration rely heavily on the interconnects redistribution layer (RDL) for this routing.

The most promising option to further reduce the interconnect dimensions relies on a dual-damascene process using photo-sensitive polymers as dielectric.

Unfortunately, using a polymer as a dielectric presents serious reliability challenges as polymers are generally unable to block the diffusion of oxygen, resulting in copper oxidation even at temperatures below 200 °C. Additionally, copper oxidation is not self-limiting.

As the critical dimensions of the lines are scaled down, high rates of oxidation are therefore a major reliability concern.

Recently the possibility of protecting the copper lines from oxidation through very thin ALD layers was demonstrated. For example, HfO₂ films as thin as 9 nm have been shown to effectively prevent copper oxidation during aggressive corrosion stress tests. Nevertheless, despite their minimal thickness, these dense films, deposited on the full surface of the wafer, are known to lead to mechanical stress. Ultimately, this stress can result in delamination and fracture during the next process steps.