As extreme ultraviolet (EUV) lithography progresses to a mature high volume manufacturing technology, innovations are still required to meet the device scaling and performance requirements. While many of these innovations may take the shape of integration changes, plasma processing will still play an important role in shaping the next generation of technology. In order to advance plasma processing for the next nodes, we must start looking at plasma process development beyond the standard process tuning knobs. New chemistries and techniques must be thoroughly investigated and out of the box thinking must be applied. The applications to which plasma processing can benefit single exposure and multi-patterning techniques are vast, ranging from roughness and profile improvements to the enablement of new integrations techniques.

In this presentation, we will discuss a few of the many innovations we have investigated to overcome the challenges of EUV patterning. It is well known that EUV lithography suffers from stochastically driven defectivity, in particular, feature breaks and bridges, and high roughness.¹ Plasma based process improvements, including etch process co-optimization with films, and selective deposition, have provided critical improvements in this area.^2,3 Processes such as selective deposition also open the door for innovative integration schemes that would otherwise be inhibited.⁴ The advent of high-NA EUV lithography will present its own unique challenges, including new materials, in particular metal containing resists, and even smaller feature sizes, in addition to the known challenges of the current generation of EUV lithography.⁵ Advanced plasma processing, especially etch, will play an important role in overcoming these hurdles.

1. L. Meli, J. Church, A. De Silva, K. Petrillo, D. Goldfarb, S. Stieg, R. Lallement, D. Lea, M. Burkhardt, N. Felix, and C. Murray, Proc. SPIE, 116090P (2021).
2. L. Meli, K. Petrillo, A. De Silva, J. Arnold, N. Felix, C. Robinson, B. Briggs, S. Matham, Y. Mignot, J. Shearer, B. Hamieh, K. Hontake, L. Huli, C. Lemley, D. Hetzer, E. Liu, K. Akiteru, S. Kawakami, T. Shimoaoki, Y. Hashimoto, H. Ichinomiya, A. Kai, K. Tanaka, A. Jain, H. Choi, B. Saville, and C. Lenox, J. Micro/ Nanolith. MEM MOEMS, 18, 011006, (2019).
3. J. Church, K. Lutker-Lee, L. Meli, E. Miller, and A. Raley.AVS (2021).
4. K. Lutker-Lee, E. Richardson, D. O’Meara, and A. Raley, Proc. SPIE, 11615, (2021).
5. Thiam, J. G. Santaclara, J-H. Franke, F. Schleicher, R. Blanc, P. Bezard, A. Moussa, P. Wong, E. Hendrickx, and M. J. Maslow, Proc SPIE, 118540A (2021).

Even though Extreme Ultra Violet (EUV) lithography has the advantage of implenting a finer pattern compared to ArF immersion lithography due to the use of 13.5 nm instead of 193 nm as the wavelengh of the light source, due to the low energy of EUV light source, EUV resist has a thinner thickness than conventional ArF resist and it is more vulnerable to radiation damage received during the etching because of its low etch resistance and also tends to have a problem of low etch selectivity. In this study, the radiation damage to an EUV resist during the etching of hardmask materials such as Si₃N₄ and SiO₂ using a CF₄ neutral beam has been investigated and the results were compared with those etched by a CF₄ ion beam. The results showed, for the etching of the same EUV resist thickness, less line edge roughness, less critical dimension loss, and higher etch selectivity to the hardmask materials such as SiO₂ and Si₃N₄ were obtained for the CF₄ neutral beam etching compared to the CF₄ ion beam etching.

Key word : extreme ultraviolet (EUV) lithography, extreme ultraviolet (EUV) PR, low damage, line edge roughness (LER), critical dimension (CD), neutral beam etching(NBE), ion beam etching(IBE)

Extreme Ultra-Violet (EUV) systems achieve smaller feature sizes in microelectronics processing by deploying photons with ~10 nm wavelength for photolithography. There are several advanced techniques for generating EUV photon beams; one of which is ablating and ionizing tin droplets with pulsed lasers. Excited tin ions emit photons with a 13.5 nm wavelength. These photon beams are collected and focused with a collector mirror, and then photons are transferred to the scanner unit. The lifetime and reflectivity of the collector mirror decline with time due to deposition of tin. An in-situ cleaning technique of tin deposited on the optics involves pumping H₂ into the chamber. H₂ gas does not substantially attenuate the EUV beams, but the photons have enough energy (92 eV) to create an H₂ plasma through photoionization and photodissociation reactions. Hydrogen radicals then etch the tin deposits by producing stannane, a volatile gas which can be pumped from the chamber. The most significant loss mechanism for hydrogen radicals is recombination reactions on the walls. The addition of a small amount of oxygen helps decrease the wall losses of hydrogen radicals by production of the water vapor. The water vapor adsorbs on surface sites, which blocks recombination of H atoms.

In this paper we discuss results from a computational investigation of the low-pressure H₂-O₂ plasma produced from EUV photon beams in a generic EUV photolithography tool using the Hybrid Plasma Equipment Model (HPEM). The densities of radicals, ions, and excited species, their fluxes (including energy-and-angular distributions) to the chamber walls, and the surface coverage fractions will be discussed. For pressures of a few to tens of Pa and hundreds of Watts EUV power, the addition of oxygen increases hydrogen radical density in the chamber and decreases the surface loss of hydrogen radicals. The consequences of oxygen fraction, pressure, and photon intensity on plasma properties and surface mechanisms will be discussed.

Work supported by Samsung Electronics and the National Science Foundation.

As the critical dimensions (CDs) decrease to a few nanometers while the aspect ratios increase beyond 100, the cost of process development significantly increases and the performance of the plasma etch process is critical to the success of ramping a new technology node toward profitable high-volume manufacturing. In this paper, a plasma dry etch simulator developed at KLA, ProETCH^® [1], has been applied to investigate a defect that arises in an overlay metrology target in DRAM during shallow trench isolation (STI) etch patterned using self-aligned double patterning (SADP). SADP process is characterized by performing lithography at a pitch that is two times larger than the desired pitch and is followed by spacer deposition, a spacer etch-back and core etch processes. A challenge of this scheme is that each process introduces some non-uniformity, leading to variations in, for example, the hard mask that is eventually utilized for the final etch. One typical defect is the pitch walk, which manifests different trench openings between the pillars. This periodicity is indicative of the SADP process and corresponds to where the resist core line is patterned initially. The principal objective of this work is to investigate the influence of hard mask irregularities on the STI etch process evolution ProETCH. The mechanism of silicon etch by Ar/Cl₂ plasma was developed with the experimental data (cross-section SEM images) as reference. The variations in the hard mask that arise during the SADP process were found to have a significant impact on the printability of these targets. The differences in trench openings result in aspect ratio dependent etch (ARDE), which could be mitigated by modulating the plasma fluxes to the surface.

[1] P. Panneerchelvam et al., Trilayer hard mark lithography and etch for BEOL manufacturing, SPIE Advanced Lithography, San Jose, California, USA, April 2022.

High aspect ratio (HAR) ONON channel etch is a very complex and challenging step in 3DNAND flash memory production and the challenges increase with increasing vertical stack height and reducing pitch sizes. A variety of fluorocarbon gases are used to etch the alternating layers of SiO2 and SiN selective to the mask while maintaining a vertical profile. Control of sidewall polymer formation and its properties such as electrical conductivity are potential pathways to overcome undesirable patterning feature distortions such as bowing, twisting, tilting, and sidewall electrostatic interference i.e “charging.”

We demonstrate that engineering the polymer for both its composition as well as conductivity can be accomplished by modification of the chemistry mixture that is used in the plasma process. Characterization of the polymer is done using XPS, SEM, EDS, and current-voltage (I-V) measurements in a variety of simplified test structures to elucidate the properties of the polymer on the etch front and the sidewall. Understanding of the composition of polymers from standard fluorocarbon chemistries including C4F8 and C4F6 along with new fluorocarbons gases will be presented showing changes in the C/F ratio of the polymer on the sidewall at different aspect ratios as well as the difference in polymer between the etch front and the sidewall of test structures. In addition, Quadrupole Mass Spectrometry (QMS), a powerful tool, is implemented to identify positive ion fragments that might be present inside the plasma. Furthermore, such details can elucidate the deposition and etching characteristic of these ions during HAR etching. The combination of polymer characterization and analysis of gas species via QMS can give us a better understanding of the etching process. Finally, new work in improvement of the polymer conductivity using new etching gases will be presented demonstrating >100x improvement in the polymer conductivity.

Nowadays, new architectures and structures for advanced Logic and Memory devices come with new etching processes and challenges. Among them, anisotropic etching of Si dielectric layers with very high selectivity to the mask, defect free soft-landing to the under layers, and profile control (no bowing, twisting, scalloping, clogging, loss in critical dimensions, and etch stop) is needed for the realization of advanced patterns (e.g. gate spacers, SADP, SAQP, high aspect ratio ONON and contact holes). These layers, such as SiO₂ and SiN, are standardly etched using fluorocarbon-based plasmas that involve multiple simultaneous reactions and phenomena. A key one is passivation, used to suppress lateral etching and damages. Etchants such as CF₄, C₄F₈, C₄F₆, CHF₃, CH₃F, etc. allows the etching of SiO₂ and SiN through the generation of mixed and polymer layers which, assisted by ions bombardment, lead to desorption of volatile byproducts such as CO_x, COF_x, SiF_x, NH_x and HCN. Same polymers generated by these standard gases are also used to protect structure’ sidewalls during the etching, where the contribution of ion bombardment is much weaker. Nevertheless, the lack of polymer conformality on the sidewall and its different interactions with the mask or under layer materials strongly contribute to the appearance of etching defects that need to be mitigated.

To mitigate these drawbacks, we investigated the potential of new hydrofluorocarbons-based gases for the etching of high aspect ratio structures, such as 3D NAND holes or DRAM pillars, as well as gate spacers. Not only do these new etchants outperform the ones currently used (higher selectivity to the mask, better profile control, etc.) but they are also more environmentally friendly with lower Global Warming Potentials (GWP). In-depth studies (e.g. polymer deposition, composition, OES, etc.) have shown that these improved performances are linked to the unique polymerization properties of the molecules on the mask and structure sidewalls. The observed differences in profiles etched by two isomers demonstrate the importance and impact not only of the chemical composition but also the molecule structure and design on etch performances. In this example, a first isomer leads to more polymer deposition on the bottom of HAR holes, while polymer generated by a second isomer deposits more on the top. A second example, using a similar approach, demonstrates how the usage of new hydrofluorocarbons in Plasma-Enhanced Atomic Layer Etching process allow reducing SiN spacers footing with a soft-landing on Si channel. Utilizing these lower GWP gases lead to a process with better profile control and similar throughput.

Benefiting from the interdigitated back contact (IBC) architecture and the silicon heterojunction (SHJ) technology, IBC-SHJ solar cell currently holds the record efficiency for single-junction solar cells based on crystalline silicon [1]. However, the necessity of performing photolithographic patterning steps to form the interdigitated carrier collection zones makes this architecture unsuitable for low-cost, high-throughput manufacturing processes.

We present here a novel method that allows the creation of the interdigitated carrier collection zones for IBC-SHJ solar cells by PECVD process in a maskless and contactless manner. This method involves using a slottedpowered RF electrode, which has parallel slits in it, in a custom‐designed CCP-PECVD chamber. By keeping the RF electrode in close proximity to the substrate surface (down to sub-mm range), plasma will selectively light only within the slits, thus mimicking the patterns on the electrode [2]. Deploying this patterned plasma process with an etching gas mixture (NF₃/Ar) on a well-designed silicon thin film stack, the interdigitated carrier collection zones required for an IBC architecture have been obtained.

Multiple structural and electrical characterizations (profilometry, spectroscopic ellipsometry, photoluminescence, photovoltage mapping, and secondary ion mass spectroscopy) are performed throughout the whole process flow, which gives good guidance for the processes optimization. The J(V) characteristics of the solar cells fabricated by this method will be presented, and the importance of an additional step to remove the damaged layer on the surface left by the patterned etching process will also be discussed.

References
[1] K. Yoshikawa, et al., “Silicon heterojunction solar cell with interdigitated back contacts for a photoconversion efficiency over 26%”, Nat. Energy, 2, 17032 (2017).

[2] R Léal, et al., “Maskless and contactless patterned silicon deposition using a localized PECVD process”, Plasma Souces Sci. Tech. 29, 025023 (2020).