AVS2016 Session PS-MoM: Advanced FEOL/Gate Etching

Sidewall image transfer (SIT) is an indirect patterning method that involves the deposition and etching of silicon nitride spacer to achieve sub-lithographic linewidths. Current approaches to etch silicon nitride spacer face two main challenges ­­— footing and corner rounding. Solution to these problems requires a non-polymerizing chemistry that must be anisotropic and yet avoids the adverse impact of ion-bombardment. To this end, an alternative etching process based on the modification of silicon nitride by light ions followed by the selective removal of the modified layers by DHF has already been reported [1]. However, this process uses non-compatible etch techniques (dry and wet etch). To overcome this challenge, we have developed a plasma-based alternative to DHF. After the spacer etch, isotropic etching of silicon with infinite selectivity to the nitride spacer and underlying oxide is required for mandrel pull. Current methods used to etch silicon involve the redeposition of etch by-products and bombardment by energetic ions. Therefore, these processes are not isotropic and result in footing and significant damage to the underlying material.

In this presentation, we will demonstrate the feasibility of our approach to etch silicon nitride spacer without any footing and corner rounding. In addition, damage to the underlying oxide is negligible. We will also discuss the effects of non-idealities such as scattering and deflection of ions during the hydrogen plasma treatment and the incoming topographical defect on the etch profile. In addition, we will demonstrate the feasibility of novel strategies for isotropic etching of silicon with infinite selectivity to oxide, nitride, and other materials. These processes are by-product free and we do observe any footing. In addition, damage to the underlying material is negligible.

1. N. Posseme,O. Pollet, and S. Barnola, Appl. Phys. Lett., 105, 051605 (2014).

Low-k spacer materials such as SiBCN have garnered attention recently for advanced technology nodes due to their controllable electrical conductivity, low thermal expansion coefficient and potential for reducing loading capacitance. [1] Of particular concern in a spacer etch process is reducing the damage caused to materials such as the bottom oxide (BOX) and the underlying fins in FinFET systems. This is often a difficult challenge owing to the tight pitches and widely disparate critical dimensions (CDs) between the fin and gate geometries.

We present a spacer etch process using a novel high-selectivity gas chemistry that shows minimal damage in a FinFET system with SiBCN spacer deposited over SiGe fins. In addition to reduced damage compared to a conventional CH₃F/O₂ plasma chemistry, we also demonstrate greatly improved throughput even at low duty cycles by taking advantage of the unique chemical properties of the gas. We show <5nm SiGe fin loss for long overetch values, with minimal box loss as measured by high-resolution transmission electron microscopy (TEM).

The effect of pulsed plasma parameters are analyzed via optical emission spectroscopy (OES) in an attempt to define the etching mechanisms, as well as explain the difference between blanket etch conditions and patterned features. We focus on the effect of He dilution within the plasma as well as the effect of phase difference between source and bias for synchronous pulsing cases.

References:

[1] R.G. Southwick et al., IEEE International Reliability Physics Symposium pp. BD.2.1-2.4, 2014

Silicon nitride (SiN) is an essential film in complementary metal oxide semiconductor devices. The amount of hydrogen contained in SiN films depends on the process conditions used in chemical vapor deposition (CVD), and strongly affects the etching properties of etching rate (ER), C-F polymer thickness (T_C-F), and damage. Therefore, revealing the mechanism of how hydrogen influences etching is very important to predict and control damage distribution considering the etching profile, and to develop etching processes with high selectivity for SiN over SiO₂.

To model SiN etching under the effect of hydrogen, we performed experiments using a dual-frequency capacitively coupled plasma system. We prepared three kinds of SiN_x:H_y films with y = 2.6%, 16.8%, and 21.9% (denoted as LP-SiN, Low-H SiN, and High-H SiN, respectively) on Si substrates using different CVD processes. The films were treated with CH₂F₂/O₂/Ar plasma under a gas pressure of 20 mTorr and Vpp of 350 V, for which we measured ER and T_C-F values. We also measured plasma and surface conditions using various monitoring techniques. We analyzed the results through a first-principles calculation with VASP [1].

We found that for the low CH₂F₂/(CH₂F₂+O₂) ratio where few C-F polymer layers existed, the ER values of High-H SiN were 20%–40% smaller than those of LP-SiN and Low-H SiN. In contract, inverse behavior was observed in the case of a high CH₂F₂/(CH₂F₂+O₂) ratio. Considering variation of OES data and reactivity estimated by the VASP calculation, under the assumption that the etching front consisted of two layers (C-F polymer layer and reactive layer) [2], not only reaction between the outflux of H from the reactive layer and F from plasma but also termination of Si dangling bonds by H seems to cause variation of the ER value when the CH₂F₂/(CH₂F₂+O₂) ratio is low. Because a C-F polymer layer of moderate thickness existed over the reactive layer at high CH₂F₂/(CH₂F₂+O₂) ratio, some H was consumed by reaction with C in the polymer layer, which weakened the effects of H such as deactivation of F and termination of Si dangling bonds. This seems to lead to the inverse behavior observed at high CH₂F₂/(CH₂F₂+O₂) ratio.

We formulate the above effect of H and include it in our SiN surface reaction model using the 3D voxel-slab method [3], reproducing ER and T_C-F values. We also demonstrate SiN side-wall etching of fin-type field-effect transistors and discuss how to control etching profile and damage distribution.

[1] G. Kresse and J. Furthmüller, Phys. Rev. B 54, 11169 (1996).

[2] M. Matsui et al., J. Vac. Sci. Technol. A 19, 2089 (2001).

[3] N. Kuboi et al., J. Vac. Sci. Technol. A 33, 061308 (2015).

Moore’s law extension in the semiconductor industry requires processing of features at nanometer scale. Approaching sub-10NM technological fabrication we face more stringent requirements to the etch process (high anisotropy and high selectivity to the mask films).

We present peculiarities and new challenges of 3D gate etch processing in halogen-based plasmas. These include by-product -free etching of narrow features, “FIN-Gate” corner residue removal, prevention of merging of the neighboring gates and advanced selectivity control to the FIN oxide. To combine all these in one process, we need multiple unique steps responsible for certain stages of etching. The etching mechanisms and dependence of the etching properties (selectivity, anisotropy and etch rate) on the plasma discharge parameters (electron temperature, ion and radical densities, ion energy) will be described for each step. We have successfully approached the 7NM technological node at aspect ratios and, etch depths up to 6:1 and 160 nm, respectively, with a potential for the next technological generation.

An additional subject of discussion is related to surface-plasma interactions between charged and neutral species in HBr plasmas. Formation and deposition of non-volatile bromine-containing by-products SiBr_x (x=1,2) and SiBr_xO_y can result in clogging of narrow features, etch profile distortion, limited etching depth and residual Si at high aspect ratios. These non-volatile species are accumulated on the process chamber wall, desorb to the gas phase and can re-deposit on the processed wafer for long times – well after the main etch process is over. We demonstrate the importance of the chamber wall chemistry condition and plasma discharge parameters in formation and re-deposition of these species. Chamber wall surface cleaning by fluorine-containing plasmas and lowering the source power resulted in significantly smaller amounts of by-product and can be used as profile control knobs in the process.

Continued scaling of FinFET technology introduces unique challenges with respect to patterning high aspect ratio structures. In addition to the traditional challenge of etching a gate with uniform sidewall and cross wafer uniformity, new challenges are introduced as a result of the reduction of inter-gate spacing. Maintaining selectivity to dielectrics during Si etch can result in profile degradation due to etch polymer by-product pinch-off. Low polymer producing chemistries can prevent this pinch-off, but with the cost of unacceptable Fin erosion. Furthermore, gate profile and pitch control can have significant impact on down stream process stability and may result in downstream gate bending. In this paper, the unique challenges caused by gate pitch scaling will be explored with respect to not only their impact on downstream functionality, but also to the gate etch itself.

FinFET based CMOS technologies continue scaling down in Fin Pitch1-3. Self-aligned double patterning (SADP) and Self-aligned quadruple patterning (SAQP) have been used to form tight Fin pitch structure. Device requirements and layout constraints can result in the need to cut different numbers of fins, which form variable spaces between fins, but a consistent Fin height must be maintained. In addition to the space variability, gap fill oxide density variations are observed depending on local feature density. A key process for defining the height of the active fin for Bulk Substrates is the Fin reveal process

Such space and film density variations between Fins introduce significant challenges for the Fin reveal process, especially in the sub 40nm Fin pitch range. In this paper, we show initial results from a hybrid Fin reveal process, that combines anisotropic etching with reactive clean techniques. We show the ability to maintain fin reveal depth uniform across feature densities and quality.

The conventional Si CMOS technology recently encounters difficulties to maintain its dimensional scaling owing to the high power consumption of logic chips. The planar MOSFET has already evolved to a FinFET, a three dimensional device architecture which provides lower leakage current. New channel materials are now therefore considered to continue the transistor scaling and enable higher device densities with faster logic switching and lower power consumption. The III-V semiconductors which present electron velocities ten times higher than the silicon, are seriously considered as N-channel materials in a FinFET architecture for the sub-10nm technological node. To complete this integration, the development of plasma etching processes dedicated to the III-V fin patterning is necessary. The major challenge for nanometer-scale III-V finFET definition by plasma etching is the realization of vertical sidewalls with a high quality surface.

In this work, we address this challenge by undertaking a systematic investigation of dry etch processing for InGaAs fin formation, with the aim of obtaining high resolution fins with vertical sidewalls and clean etch surfaces. The InGaAs layers have been grown by MOCVD on 200mm Si wafer and photoresist lines with dimensions ranging from 20 to 100nm have been patterned by ebeam lithography. The plasma etching experiments are carried out on a 200mm etching platform from AMAT composed of two inductive coupled plasma reactors, whose one is equipped with a hot cathode. The performance of Cl₂ and CH₄ based plasma processes at 50°C and 200°C have been evaluated and compared in terms of anisotropy, surface roughness and plasma induced chemical damages. A particular attention is paid on the chemical and physical damages induced on the pattern sidewalls. The pattern profiles are characterized by electron microscopies. The sidewalls roughness is measured by AFM using a homemade setup where the sample is tilted to allow the tip to scan the sidewalls. The sidewalls chemical composition and stoichiometry after etching is analyzed by nanoauger spectroscopy. We also investigate restoring processes to mitigate the etch-induced sidewalls damages by combining oxidation and wet removal steps. Finally, we propose a new method to pattern the III-V fins without generating etching damages. It consists of a two-step process, starting with a surface modification by a He or H₂ plasma implantation followed by a wet cleaning to remove the modified surface without damaging the non-modified one. This method appears promising to etch the III-V fin without damaging the fin sidewalls and will be benchmarked to conventional plasma technique.