AVS2015 Session EM-WeA: Interconnects: Methods and Materials for Removing Connectivity Constraints

Electromigration (EM) failure is always one of the key challenges of BEOL Cu interconnects. The continuous shrink of Cu feature size leads to higher current densities, which lower EM lifetimes. The interface between Copper and dielectric cap has been identified as the key diffusion path for copper atoms, and the adhesion of the interface is critical to EM performance. Different methods developed to improve the adhesion between copper and dielectric cap interface. One method of improving the adhesion has been the use of alloy seed, CuMn or CuAl. Mn (Al) will segregate and bond chemically to the copper and dielectric cap interface during dielectric cap deposition which can improve the adhesion of the interface and suppress Cu atoms migration along the interface under current stress. An alternate method of improving the adhesion is to have a self-aligned CoWP Cap or Selective CVD Co Cap on top of Cu which was developed for more stringent EM requirement of advanced nodes, such as 32nm, 20nm and beyond. Compare to self-aligned CoWP plating process, selective CVD Co Cap has higher selectivity and more compatible with porous ultra low k film. In this paper, we focus on interdiffusion characterization of selective CVD Co cap and copper. Co/Cu interdiffusion of cobalt films with different precursors are thoroughly evaluated and compared. Nitrogen content in Co film which enriches the grain boundaries due to low solubility in Co was identified as the key knob to control Co/Cu interdiffusion. Less nitrogen in Co film results in more copper diffusion. Better EM results on 20nm groundrule test structures demonstrated with higher nitrogen in Co film. Thermal anneal with H2 gas was found to be able to reduce nitrogen content in Co film which result in more Cu diffusion. Secondary Ion Mass Spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS) and Electron Energy Loss Spectroscopy (EELS)/ Energy Dispersive X-ray Analysis (EDX) line scan were used for Cu diffusion characterization which clearly show Cu signal on top of Co film. A novel analytical technique of SIMS has been developed to characterize nitrogen content in Co film that CoN was selected as nitrogen detection molecular since nitrogen has some interaction with Co within the film.

Nanocarbons such as carbon nanotubes (CNTs) and graphene are candidate materials for next-generation integrated circuit technologies due to their high current-carrying capacities and excellent electrical, thermal, and mechanical properties [1,2]. The key performance-limiting factor continues to be the high contact resistance at the interface with metal electrodes [3]. Metal depositions are frequently used during post-fabrication contact engineering for these nanocarbons to mitigate the high resistances between these materials and metal electrodes, with various degrees of success in achieving stable low-resistance contacts [4]. We have fabricated test devices for CNT vias, and measured their current-voltage (I-V) characteristics [5]. In this study, post-fabrication contact engineering is performed using electron-beam induced deposition of tungsten (EBID-W) [6] to improve the electrode contacts and hence reduce the total device resistance.

Fabrication of these via test structures without top contact metallization was described elsewhere [5]. In the present study, EBID-W is used to form the via top contacts (Fig. 1). From I-V and resistance measurements on 500 nm x 500 nm CNT vias with and without EBID-W top contact metallization, the effect of EBID-W contact on resistance reduction is clearly demonstrated (Fig. 2). While similar improvement can be obtained by current stressing without contact metallization [5], such technique would introduce an additional thermal cycle to the chip fabrication process and hence undesirable. On the other hand, the resistance of a via with W top contact is shown to have reached its minimum which is unaffected by further annealing (Fig. 3). Thus the contact resistance of the CNT via is indeed improved by top contact metallization with W, and that the resistance is stable. Without increasing the thermal budget from current stressing in chip fabrication, the use of EBID-W for via top contact metallization could facilitate the eventual functionalization of CNT via interconnects.

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To enable the continued scaling of interconnect layers for the 10nm node and beyond an increased number of materials and integration challenges will need to be addressed. Historically, interconnect dielectric materials have been broken down into Interlayer Dielectrics (ILDs) and Etch Stop (ES) / Hard Mask (HM) materials. The ILD layer is the major driver in capacitance improvement, while the ES layer enables patterning and acts as a diffusion barrier. In this paper, we will discuss two major challenges: (1) Pathways for the integration of porous low-k ILDs, and (2) Development needs for ES materials to enable improved patterning options.

The industry continues to work on the integration of low-k ILDs, but the momentum to implement these films has slowed in recent years due to the challenges of working with porous thin films. Low-k ILDs (k~2.0) exhibit 40-50% porosity with an interconnected pore network. The increased porosity can lead to damage and increased roughness during patterning, and can allow precursor penetration during the metal barrier deposition. To mitigate the problems of integrating a porous ILD, we have utilized the approach of pore stuffing. In this process, a sacrificial material is infiltrated into the pores of a fully cured ILD. The resultant film is non-porous with increased mechanical properties.

In this paper, we will discuss the challenges of finding a pore stuffing material that can fill the pores of the ILD, remain in place during dual damascene processing and can then be removed from the low-k ILD post metallization and CMP. In addition, we will show how pore stuffing improves trench profiles, and how it prevents metal penetration during barrier deposition. Finally the successful implementation of this process will be demonstrated and integrated capacitance improvement will be presented.

In a classic dual damascene flow, the ES layer is used as a diffusion barrier and as a patterning stop between ILD layers. To enable more advanced patterning and integration schemes, the role of these materials needs to be expanded. Specifically, there may be situations where multiple ES/HM materials are needed and with high etch selectivity to each other (>20:1). Etch selectivity values for typical materials (e.g. nitrides, carbides, amorphous silicon, metal hard masks and carbon hardmasks) are not currently sufficient. Development of new material options, deposition techniques and etch processes are needed. In this paper, we will discuss the current needs for new ES\HM materials and novel etch technology, along with our current progress toward this challenge.

Porous ultra-low k (ULK) dielectric films with high porosity and larger pore size (k<2.4 and beyond) pose a serious challenge for their integration into next-generation microchips. In this paper, we report the formation of a thin layer of SiCxNy based pore sealing film deposited by UV assisted CVD. This film when deposited on damaged ULK surface assists in sealing the interconnected pores to prevent diffusion of metal liner and barrier metal precursors during the subsequent metallization steps. In addition pore sealing also enables an efficient sidewall protection to ULK thereby reducing its degradation by radical penetration during subsequent wet clean processes. A side benefit of this method is replenishment of depleted methyl species in damaged subsurface sites thereby improving hydrophobicity and recovery of k damage. A very thin pore seal film ~15 Ang is found to be sufficient to prevent metal precursor diffusion into a porous ULK k2.4 material. Porosimetry and backside SIMS were used to assess sealing behavior on surface pores of damaged ULK. On pattern wafers pore sealing treatment has been shown to significantly improve VBD and TDDB of k2.4 ULK to a level comparable to that observed for industry standard ULK k2.55 material. No structural change is observed in pattern CD for up to 15A of pore-seal deposition. Although this deposition is highly selective to surface sites available on damaged ULK, a thin layer (i.e. < 5A) of pore seal residue formed on Cu via bottom has been shown to be completely removed by typical CuOx wet clean solutions. Kelvin via measurements on structure wafers show that pore-seal with wet clean yields comparable via resistance as compared to wafers without pore-seal.

Due to the conformity required for deposition of metals in high aspect ratio vias, Physical Vapor Deposition is replaced by techniques from the Chemical Vapor Deposition (CVD) family. Conformity wise, the Atomic Layer Deposition (ALD) appears to be the best of the CVD techniques, but the low throughput is dissuasive for layers thicker than 10nm. At the edge between CVD and ALD, the Fast Atomic Sequential Technique (FAST) developed and patented by Altatech, enables deposition of layers with conformity close to the ALD at a higher throughput.

Through Silicon Vias are extensively used for interconnections and necessitate highly conductive materials in holes of aspect ratio higher than 10. Of all low-resistivity metals, namely Ag, Al, Au, Cu and W, studies showed that Cu is the best for filling trenches. Therefore, both the metal and the technique used are imposed, i.e. Cu deposition by CVD is the most suitable solution.

The main obstacle for a complete adoption of Cu as an interconnection metal is the difficulty to clean the chamber after process, since Cu cannot be etched by the usual fluorinated in-situ dry etching processes.

Successful deposition of conformal Cu layer was performed in vias with an aspect ratio of 10, using Altatech AltaCVD deposition chamber and a commercially available Cu precursor. Optimised deposition parameters resulted in low resistivity Cu, down to few µΩ.cm, with deposition rates higher than 100 nm.min^-1. Plotting the deposition rate depending on the substrate temperature highlighted an Arrhenius law behaviour, which in turn provided the optimal deposition temperature. Complementary SEM observation showed Cu layer with low roughness.

Futhermore, taking advantage of the Altatech pulsed solution, FAST, an in-situ dry cleaning process was developed using hexafluoroacetylacetone (hfacH) solvent. The main scheme for Cu etching comprise one step of Cu surface oxidisation and a second step where CuO_x compounds react with hfacH solvent to form volatile species. Several approaches were assessed; the following one will be presented and discussed:

1. O₂ and hfacH introduced simultaneously in the chamber
2. Alternation of O₂ plasma and hfacH fill
3. Pulsed alternation of O₂ and hfacH fill
4. O₂ plasma and pulses of hfacH

Optimising and understanding the influence of each process parameter was made possible by the use of a Residual Gaz Analyzer (RGA) and an Optical Emissions Spectrometer (OES). Cleaning efficiency at the particle generation level of all the approaches are compared, after few microns of Cu deposition and a chamber clean.

Finally, the efficiency of the most promising approach will be investigated on different chamber coatings.

With the continuous shrinkage of back end of line (BEOL) metal pitches of sub-10nm technology node, integration with ultra-low κ (ULK) film becomes even more challenging. In comparison to traditional PECVD ULK films introduces pore through deposition with porogen precursor followed by UV or E-beam exposure to generate porosity , a new single precursor based ULK (ultra low κ) film has been formed without porogen and show promising on the sub 10nm technology road map . In this paper, we will use transmission Fourier Transform-Infrared (FTIR) spectroscopy, X-ray photoelectron spectroscopy (XPS) and Ellipsometric Porosimetry (EP) etc. to investigate the impact how different UV conditions will modify chemical bondings, film composition, pore structure and porosities. The role of UV in this new type of ULK film formation will be studied while difference UV conditions include UV bulbs and UV curing vacuum ambient etc. Film mechanical properties as well as electrical properties will be thoroughly compared. The interaction with downstream integration process steps, such as plasma induced damage and selectivity to MOCVD cobalt capping will be examined.

2. B. Bittel, P. Lenahan, and S.W. King, Appl. Phys. Lett. 97, 63506 (2010).