In this talk we present a multi-element computational approach for quantitatively describing atomic interdiffusion within a random-alloy SiGe wafer subject to a patterned stress field imposed by an indenter array applied to its surface. The model, and the associated parametric investigations we carry out, are motivated by a recently-proposed approach for forming ordered arrays of heteroepitaxial Ge quantum dots (QD) on semiconductor substrates in a scalable and robust manner. In this approach, patterned compositional redistribution of Si and Ge atoms is driven by an applied stress field under thermal annealing. The resulting compositional heterogeneity is shown to induce an internal stress field in the SiGe substrate wafer that persists after the indenter array is removed, thereby effectively “transferring” the stress pattern of the indenter into the substrate. The transferred stress pattern, which we study in detail as a function of several parameters including indenter geometry and thermal annealing schedule, is then used to drive patterning in a subsequent Ge deposition step.

The interdiffusion model is based on a combination of lattice kinetic Monte Carlo (LKMC) and static energy minimization. The LKMC simulation is propagated using rates for atomic diffusion that depend explicitly on local values of stress, composition, and temperature. The dependence of atomic diffusion on composition is regressed to experimental data while the stress dependence is described using the theory of activation volumes [1]. The stress field is updated quasi-statically using a separate energy minimization routine with forces computed based on a Tersoff interatomic potential for the Si-Ge system [2]. The atomic stresses and identities are then smoothed to generate continuous fields that are used as input into the LKMC simulation.

Using our model, we establish that atomic redistribution is feasible for reasonable indenter forces and annealing times and temperatures. We compute the corresponding internal stresses in the compositionally patterned film for several different annealing conditions and show that these stresses are likely to be large enough to influence subsequent Ge quantum dot nucleation and growth. We also compare our results to recent experimental measurements.

References:

[1] M. J. Aziz, Applied Physics Letters 70, 2810 (1997).

[2] J. Tersoff, Physical Review B 39, 5566 (1989).

Recently, a scanning tunneling microscopy (STM) technique to fabricate atomically-precise dopant-based nanoelectronics in Si has been developed. Phosphorus donors are placed via an atomic-precision template formed by STM H-depassivation lithography, then capped with epi-Si and lastly metal contacts are made to the buried donor layer using conventional microfabrication. New challenges are introduced with this approach that center around difficulties to locate and characterize the pattern of buried donors. In this talk, we show that scanning capacitance microscopy (SCM) can image these buried donor nanostructures with sub-100-nm tip-limited resolution. The technique is used to successfully locate and characterize buried donor nanostructures relative to surface alignment marks. This approach relaxes alignment requirements for the STM lithography step and can offer improved alignment of subsequent metallization steps. The SCM technique is also used to nondestructively image the shape of the electronic carrier distribution and characterize the relative doping levels. This work, performed in part at the Center for Integrated Nanotechnologies, a U.S. DOE Office of Basic Energy Sciences user facility, was supported by Sandia's Lab Directed Research and Development Program. Sandia is a multi-program lab operated by Sandia Corp, a Lockheed-Martin Company, for U. S. DOE under Contract DE-AC04-94AL85000.

The relentless increase in both density and speed that has characterized microelectronics, and now nanoelectronics, will require a new paradigm to continue beyond current technologies. One proposed such paradigm shift demands the ultimate control over the number and position of dopants in a device, which includes quantum information processing and variety of semiconductor device materials and architectures aimed at solving end-of-Moore’s law issues.

Such a work requires the development of a tool for the design of atomically precise devices on silicon and other surfaces, in hope of studying the effect of local interactions between atomic-scale structures, their microscopic behavior, and how quantum mechanical effects might influence nano-device behavior in very small structures. Demonstrations of remarkable 2D nanostructures down to single atom devices are reported here thanks to the development of scanning tunneling microscopy (STM) as an imaging and patterning tool. These include atomic-scale depassivation of a hydrogen terminated surface with an STM, toward the incorporation of dopants in silicon, and SiGe growth on strained silicon on insulator (sSOI). sSOI has been shown to be relatively insensitive to thermal relaxation and thereby provides a starting material that satisfies the requirements of both enabling high temperature surface preparation steps combined with providing a strained layer that can be capped with relaxed SiGe forming a high quality interface for gate tunable channel formation. In this talk we will present, STM and other characterization results on cleaning, hydrogen lithography, dopant incorporation and SiGe growth on sSOI.

Acknowledgments: This work was performed, in part, at the Center for Integrated Nanotechnologies, a U.S. DOE, Office of Basic Energy Sciences user facility. The work was supported by the Sandia National Laboratories LDRD Program. Sandia National Laboratories is a multi-program laboratory operated by Sandia Corporation, a Lockheed-Martin Company, for the U. S. Department of Energy under Contract No. DE-AC04-94AL85000.

A well-defined array of Ge quantum structures possesses unique electronic properties for a variety of applications, including quantum-computers and infrared photodetectors. Herein, we use simulation to predict and experiment to demonstrate the compositional redistribution of Si and Ge in the near-surface region of Si_0.8Ge_0.2 substrates by applying a spatially structured compressive stress to the substrate and thermally annealing the substrate under stress. The primary advantage of the proposed approach is that a single, reusable template is used to induce the compositional variation for multiple substrates. The compositional redistribution of Ge is predicted under purely elastic deformation, using a lattice kinetic Monte-Carlo simulation that accounts for the influence of composition, temperature, and stress on the diffusion kinetics of Ge in SiGe alloy. Atomistic stress field in a SiGe slab is computed using the Tersoff empirical potential and static relaxation. This compositional variation in turn can be used to selectively grow a 2D array of Ge quantum dots upon Ge exposure. To complement the computational prediction, the compressive stress is applied by pressing a 2D array of Si pillars against the Si_0.8Ge_0.2 substrate. Hertz contact model is used to calculate the compressive stress applied to the Si_0.8Ge_0.2 substrate under the Si nanopillars. We observe that the magnitude of compressive stress and annealing temperature determine the nature of deformation (elastic or plastic) in the Si_0.8Ge_0.2 substrate. Corresponding energy dispersive x-ray spectroscopy (EDS) shows that the compositional redistribution of Si and Ge in the near-surface region of Si_0.8Ge_0.2 substrates results from elastic deformation within a thermal annealing temperature range of 950 to 1000 °C and an applied stress range of 15 to 18 GPa. Based on nano-probe EDS, the elastically deformed compressed region shows near-complete Ge depletion and Si enrichment in atomic concentration. However, the temperature and stress exceeding the aforementioned ranges result in plastic deformation with no compositional variation. The plastic deformation depth is ~30 nm according to scanning transmission electron microscope images. We attribute the plastic deformation to (1) the localized pressure applied to the substrate under the contact area, (2) the near-surface substrate stiffness at substrate temperature, and (3) the tensile biaxial stress under the compressed region due to different thermal expansion rates of Si vs. Si_0.8Ge_0.2.

For EOT scaling below 0.5 nm on FinFETs, it is necessary to nucleate the ALD in 99% of the unit cells on multiple crystallographic faces to obviate the requirement that the oxide overgrow non-reactive unit cells. (1) DFTMD calculations of high-k/InGaAs stacks annealed at 700K show that oxide bonding to each InGaAs surface atom in each cell is critical to avoid dangling bonds creating conduction band edge states; this requires high ALD nucleation by a metal precursor density follow by oxidation of any metal-metal bonds formed during nucleation.. For III-V semiconductors, experimental STM and STS studies show the in-situ exposure of just a few hundred Langmuirs of atomic H readily removes both group V and group III oxides from 001 and 110 surfaces allowing high nucleation density of metal ALD precursors. Concurrent MOSCAP studies show demonstrate sub 0.5 nm EOT gate oxides with low defect densities on InGaAs after in-situ cleaning and high nucleation density ALD. (2) DFTMD studies of the a-Al₂O₃/SiGe(001) stack show that the SiGe(001) interface with Si termination (a-Al₂O₃/Si-SiGe(001)) has a superior electronic structure to the interface with Ge termination (a-Al₂O₃/Ge-SiGe(001). Silicon termination of SiGe should also be highly favorable for forming gas passivation of dangling bonds. For SiGe(001) a novel technique has been develop to produce surface which will mimic the good passivation properties of Si(001) by terminating the surface in a monolayer of Si-OH which will react with nearly any metal ALD precursor. (3) While group IV and III-V semiconductors can be nucleated by covalent bonds, 2D semiconductors require a different approached. DFTMD simulation studies show the metal coordination complexes can readily chemisorb on 2D semiconductor via non-bonding interaction and they can covalent bond multiple TMA molecules consistent with a submolecular nucleation density. A technique has been develop for functionalize 2D semiconductors with a phthalocyanine, and it has been demonstrated it can nucleate insulation sub 1nm gate oxide growth.

Crystalline strontium hafnate, SrHfO₃ (SHO), is an ideal candidate to study as a suitable high-k gate dielectric on Ge. SHO (a ~ 4.069 Å) has a reasonable lattice match to the Ge (001) surface (a/√2 ~ 3.992 Å), yielding a ~1.9% compressive strain in the epitaxial film. SHO shows a high permittivity (k~20) with appropriate band alignment (~1 eV offset) to Ge. In addition, the crystalline nature of the SHO film is expected to drastically reduce the interface trap density at the oxide-Ge interface. We will report our recent results on the growth, characterization, and electrical performance, of epitaxial SHO films and heterostructures for next-generation high-k dielectrics on Ge.

In our recent publication, we reported on the direct growth of crystalline strontium titanate, SrTiO₃ (STO), on Ge via atomic layer deposition.^[1] Electrical measurements of a 15-nm thick undoped STO film show a large dielectric constant (k~90), but high leakage current (~10 A/cm² at +1 eV). In the present work, the unfavorable conduction band offset (and high leakage current) of STO on Ge is circumvented by growing the Hf-based perovskite, SHO. For the growth of SHO, we employ the commercially available strontium bis(triisopropylcyclopentadienyl) and hafnium formamidinate precursors. After thermal deoxidation, the Ge substrate is transferred in vacuo to the deposition chamber where a thin film of SHO (2-4 nm) is deposited by ALD at 225 °C. Following post-deposition annealing at 700 °C, the perovskite film becomes crystalline with epitaxial registry to the underlying Ge (001) substrate. In situ x-ray photoelectron spectroscopy confirms stoichiometric to Sr-rich films with no GeO_x formation or carbon impurities.

Ex situ x-ray diffraction confirms the perovskite structure and orientation of the SHO film. Thicker SHO films (above 2 nm) appear to show a relaxed lattice constant, indicating relaxation of the epitaxial film above the critical thickness. The electrical performance of several SHO films and heterostructures will be presented. In general, the leakage current is reduced by several orders of magnitude for the SHO films versus STO on Ge. The current work demonstrates the promise for crystalline oxides grown by ALD on Ge for advanced semiconductor devices, including high-mobility Ge-based transistors.

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High k dielectric materials receive great attention in recent years due to the downscaling of metal-oxide-semiconductor (MOS) devices leading to the need in replacing the traditionally used SiO₂ gate oxide. Rare earth oxides are leading candidates as high-k dielectrics. Introduction of different elements into the bulk of such oxides can drastically alter the behavior of the MOS stack.

Here we present the results of incorporation of carbon into the bulk of Gd₂O₃ on the electrical properties of the Pt/Gd₂O₃:C/Si stack. Crystalline layers of stoichiometric Gd₂O₃ were MBE deposited together with elemental C on Si (100) substrates. Four samples with different concentration of elemental C were prepared: 0%, 0.10%, 0.67%C and 1.89%. MOS capacitors were prepared by in-vacuo (in the MBE tool) evaporating Pt through a shadow mask.

Capacitance voltage (C-V) measurements revealed an increase in the flatband voltage (V_fb) for the carbon rich sample. While the three samples with the lower carbon content all showed V_fb voltages of -0.1 ÷ +0.2 V, the sample with 1.89% carbon presented a significant increase to 2.25 V.

X ray diffraction (XRD) revealed that all the layers hold the same structure and that no orientation differences are present in the layers, ruling out the option of structural differences leading to such a change in V_fb. Time of flight secondary ion mass spectroscopy (ToF-SIMS) depth profiles revealed an uneven concentration profile for the carbon in the 0.67% and 1.89% samples. For both samples, the same concentration was found in the bulk of the layer, indicating the existence of a certain solubility limit that had been exceeded. This led to some segregation for the 0.67% sample to the inner interface while substantial segregation was observed in the 1.89% sample to the inner interface and some to the outer surface. Transmission electron microscope (TEM) micrographs show a thin amorphous interface layer that is formed between the Gd₂O₃ and Si that most likely plays a role in the capturing of the segregating carbon atoms.

We propose that the carbon segregation causes a modification of V_fb which is an important property of the MOS stack. By using carbon incorporation it might be possible to develop an effective method for controlling V_fb without changing the process or materials for any of the MOS gate components.