The continuous reduction of critical dimensions and the increasing complexity of interconnect structures has stressed the process requirements of metallization steps (i.e., deposition of diffusion barrier and metal seed, electroplating, chemical-mechanical polishing). Particularly, physical vapor deposition (PVD) of the barrier and seed relies on a limited number of process parameters (e.g., target and bias power, reactor pressure) to satisfy increasingly tighter film requirements (e.g., coverage over high aspect ratio features, control of barrier thickness, proper aperture of the seed to prevent void formation during electroplating). Computational modeling has proven an efficient means to aid the design and development of PVD metallization steps by allowing pre-silicon analysis of the effects of feature geometry and process parameters (e.g., see [1]). A continuum-based process simulator, based on a level-set solver for multi-material topography evolution, is applied to the analysis of 2 successive metallization steps, namely the PVD of barrier-over-ILD and of seed-over-barrier. Primary (e.g., distributed along the domain boundary) as well as secondary (e.g., emitted and reflected from surfaces) fluxes are accounted for through a ray-tracing technique that ensures mass conservation. In contrast to Monte-Carlo methods, which allow the description of gas phase kinetics, our solver is based on the specification of finite-rate surface reactions, which provides smooth topography evolution and is suitable for the analysis of extended domains encompassing multiple features, as needed for the analysis of within-die pattern effects. Sputtering, attachment, and neutralization reactions are accounted for between all the neutral and ionic species and the entire set of surface and bulk species in the film to allow the description of inter-material interactions (e.g., re-deposition of sputtered barrier species over the seed). The simulator is used to analyze the effects of neutral and ionic flux distributions (e.g., athermal neutrals, directional ions dependent on bias power) and the sputtering yield characteristics (i.e., energy and angular dependence) on the obtained film. Figure 1 presents snapshots of simulation results of the two-step process over a dual damascene structure. The results show that the simulation of consecutive steps is essential for the realistic description of inter-process effects.

[1] P. J. Stout, D. Zhang, and P. L. G. Ventzekc, J. Vac. Sci. Technol. A 21(3), May/Jun 2003

The performance of integrated circuits and their density has been improved continuously through the shrinking of the active devices according to Moore’s law. At the 0.25 mm technology node it became clear that new materials had to be introduced to reduce the RC of the interconnect which became a barrier to further improvement of the VLSI performance.

After IBM introduced Cu in 1997, low-k PECVD SiCOH dielectrics with a dielectric constant k=3.0 were introduced in 2003-2004 at the 90 nm node, after many other low-k dielectrics failed integration. Reduction or even maintaining of the interconnect capacitance at the decreasing dimensions of later technology nodes required the development of porous ultralow-k pSiCOH. The first generation of pSiCOH dielectrics with k=2.4 has been successfully integrated by IBM in 45 nm products, such as the Power 7 chip released in 2010. Material extendibility of porogen based pSiCOH has been demonstrated to k values as low as 2.0. However, the reduction of the dielectric constant is achieved for a given chemistry by increasing porosity in the films, resulting in a decrease of mechanical properties, degraded integrability of the dielectric, and potentially reduced reliability of the interconnect.

The original chemistry produced the pSiCOH films having a skeleton of mainly O-Si-O bonds, with nanometer sized pores stabilized by Si-CH3 groups (V1 type). These films are damaged by the integration processes and the degree of damage increases with decreasing k and decreasing pattern dimensions with each new technology node. To reduce these problems we developed pSiCOH films using precursors containing Si-CH2-Si bonds, enabling the fabrication of high-carbon (V2 type) films whose skeleton comprises Si-CH2-Si bonds in addition to the Si-O-Si. The high-carbon pSiCOH films have reduced degrees of porosity and improved pore structures as compared to the V1 type films of same k and, as a result, have higher resistance to processing damage and provide improved dimension control during integration compared to V1 pSiCOH of identical k values.

The talk will discuss the evolution of the low-k and ultralow-k dielectrics, the effects of the chemistries on the properties of the different types of the porous pSiCOH, and the behavior of such dielectrics during integration processing.

This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities.

As the semiconductor industry strives to keep pace with Moore ’s Law, new materials with extreme properties are increasingly being introduced and tighter control of these material properties is being demanded. Low dielectric constant (i.e. low-k) materials are one specific example. Lower k (< 6) a-SiC(N):H materials are desired to replace a-SiN_x:H (k > 6.5) as the Cu capping diffusion barrier layer in order to reduce resistance-capacitance (RC) delays in nano-electronic Cu interconnect structures. Typical methods for producing low-k a-SiCN:H materials consist of introducing controlled levels of nano-porosity via carbon doping during plasma enhanced chemical vapor deposition (PECVD) of a-SiN_x:H matrix materials. While lowering k, the introduction of nano-porosity can seriously compromise the moisture and Cu diffusion barrier performance of these materials. In this presentation, we demonstrate that critical thresholds in nano-porosity exist for the diffusion of water through low-k materials. Specifically, we utilize Fourier Transform Infra-Red (FTIR) spectroscopy, to show that the concentration and size of nano-pores formed in low-k a-SiC(N):H dielectric materials is controlled by the concentration of terminal Si-CH₃ bonding versus Si-C/N network bonding. We further combine moisture diffusivity measurements with x-ray reflectivity (XRR) and positron annihilation lifetime spectroscopy (PALS) to demonstrate that low-k a-SiC(N):H dielectrics become poor moisture diffusion barriers at mass densities < 2.0 g/cm³ and when the pore size approaches that for the molecular diameter of water. The implications of these critical nano-porosity thresholds on continued dielectric constant scaling of low-k a-SiC(N):H diffusion barrier materials will be discussed as well as methods for overcoming these limitations.

In the demanding microelectronics industry there is a constant need to increase circuit density in multilevel Copper (Cu) back-end-of line (BEOL) interconnects to improve the operating speed and reduce power consumption. With successive nodeon- node scaling, one approach to meet the capacitance-resistance (RC) requirements for the BEOL is through the introduction of organo silicate glass (SiCOH) materials with low dielectric constants (κ-value) as interlevel dielectrics (ILD). At the 45 nm node, porosity was first introduced into the BEOL interconnect structures in the form of porous organo silicate glass films (p-SiCOH) with ultra low-κ (≤ 2.55) to further minimize the RC delay. These ULK materials incorporate a large number of methyl groups and pores into Si-O based network structures, although the initial precursors and final properties may vary. Both the SiCOH and pSiCOH ILD films are commonly deposited by plasma-enhanced chemical vapor deposition (PECVD). Since their introduction nanoporous ULK films have significantly increased the Cu BEOL fabrication complexity. For example, porous ULK films are mechanically weak and tend to crack as a result of elastic mismatch with the substrate. Meanwhile, pore collapse and carbon depletion occur when ULK is exposed to RF-plasma during etching or ashing. Subsequent moisture adsorption leads to the increase of effective κ-value in Cu interconnects degrading RC performance. Therefore, the integration challenges of ULK are significant, such as plasma damage, chip packaging interaction, and dielectric/metal barrier compatibility issues. Careful optimization of the ULK properties is crucial for successful process integration in the 28 nm BEOL node and beyond.