The advent of the world’s first epitaxial graphene (EG) RF field effect transistors (FETs), grown on semi-insulating SiC wafers, has generated tremendous interest in the electronics community since devices can be fabricated using conventional photolithographic approaches [1]. Recently, RF FETs have shown an f_max of 14 GHz at 5 V_ds for a 2 μm gate width and better results are expected as gate widths are scaled down. To push the performance metrics for wafer-scale EG FETs significantly higher, key materials issues must be addressed. Some of these issues are morphology and thickness control, enhanced mobility, uniformity of sheet carrier density and resistivity, and substrate defects. Here we describe NRL-HRL-Penn State approach in the DARPA CERA program for forming EG via Si sublimation from SiC wafers and the impact of material issues on RF device performance will be discussed.

Epitaxial graphene was synthesized using an Aixtron VP508 reactor on the Si- and C-faces of 4H- and 6H-SiC semi-insulating 0° oriented substrates from 1225 to 1700°C and for 10 to 300 min. Samples were 50.8 and 76.2 mm wafers and 16 x 16 mm² witnesses. Both in-vacuo (10^-6 to 10^-4 mbar) and Ar ambient (50-200 mbar) sublimation conditions were investigated. Growth conditions resulted in continuous EG on Si-face witnesses < 1 nm thick as measured by atomic force microscopy, x-ray photoelectron spectroscopy and Raman spectroscopy, whereas growth on C-face witnesses could be varied, depending upon growth conditions, from island formation to continuous sheets > 10 nm thick. Using the witness samples, 300 K mobilities over 2,100 and 27,000 cm²V^-1s^-1 were found for 10x10 μm² sized Hall patterns for EG on the Si- and C-face of SiC, respectively.

The growth of EG on 50.8 mm Si-face wafers resulted in excellent relative resistivity uniformity of 2.8% and 300 K Hall mobilities up to 2,700 cm²V^-1s^-1 were found. Raman spectroscopy mapping of the 2D peak on the wafers determined: (1) the majority of the film was monolayer, (2) two layers of EG could be found at step edges and (3) EG was continuous across the wafer. RF FETs exhibited state-of-the-art ambipolar behavior such as electron field-effect mobility of 6,000 cm²V^-1s^-1 with I_on/I_off ratio of 19 and peak transconductance of 600 mS mm^-1 per 1 fF μm^-2 gate oxide capacitance. The f_T●L_g performance metric of 10 GHz●μm was established. Additionally, we will discuss our recent work on EG growth on 76.2 mm wafers as well as the impact of morphological features and Ar ambient controlled graphenization on future RF devices.

Supported by DARPA CERA (N66001-08-C-2048) and ONR.

[1] J.S.Moon et al., IEEE Electron Dev Lett 31, 260 (2010)

In this talk, we present recent progress in epitaxial graphene n-MOSFETs and p-MOSFETs on both SiC and Si substrates for graphene-on-SiC and graphene-on-Si technologies. Both graphene MOSFETs were fabricated in a self-aligned manner on 75 mm wafers and exhibited gate-controlled ambipolar characteristics. For the graphene MOSFETs on SiC substrates, the graphene was grown by Si-sublimation of Si-face 6H-SiC substrates in a commercial Aixtron VP508 epitaxial reactor. For the graphene MOSFETs on Si substrates, the graphene was synthesized by graphitizing a thin 3C-SiC layer grown on float-zone Si (111) substrates using a halogen process. Figure 1 shows sheet resistance maps of 3-inch graphene-on-SiC and graphene-on-Si wafers. Typical Hall mobility ranges from 500 to 2000 cm²/Vs depending on electron carrier density. Both graphene MOSFETs were fabricated with a gate oxide layer and metal gate stack. The gate length was 3 µm. The graphene-on-SiC MOSFETs showed excellent I-V saturation behavior as shown in Figure 2(a). Figure 2(b) shows measured ambipolar behaviors with n-type MOSFET at Vgs = 0 V, while p-type behaviors are observed at Vgs <-1.5 V. An I_on/I_off ratio of 33 was measured. Figure 2(c) shows measured peak transconductance of 600 mS/mm at Vds = 3 V. Figure 3 shows the extrinsic field-effect mobility of 6000 cm²/Vs for electron and of 3200 cm²/Vs for hole obtained at an effective electric field of ~0.27 MV/cm, approaching Dirac point. The measured graphene field-effect mobility is eight to 10 times higher than that of ITRS Si n-MOSFETs and ~80 times higher than that of ultra-thin-body SOI n-MOSFETs.

The graphene-on-Si MOSFETs are fabricated in a similar manner. Figure 4 shows measured transfer curves of graphene-on-Si MOSFETs, showing ambipolar behaviors with the Dirac point close to zero gate bias, unlike the graphene-on-SiC MOSFETs. The on-state current is measured at 50 to 125 mA/mm with I_on/I_off ratio of 3 to 2, respectively. This is the highest performance observed among graphene-on-Si technologies so far. RF performance of graphene FETs will be discussed. This work was supported by DARPA, monitored by Dr. M. Fritze, under SPAWAR contract number N66001-08-C-2048.

The views, opinions, and/or findings contained in this article/presentation are those of the author/presenter and should not be interpreted as representing the official views or policies, either expressed or implied, of the Defense Advanced Research Projects Agency or the Department of Defense.

[1] C. Berger et al., Science, vol. 312, p. 1191, 2006; J.S. Moon et al., IEEE EDL., vol 30, p650, 2009