The principal obstacle to III-V compound semiconductors rivaling or exceeding the properties of Si electronics has been the lack of high-quality, thermodynamically stable insulators on III-V materials. For more than four decades, the research community has searched for suitable III-V compound semiconductor gate dielectrics or passivation layers. The literature testifies to the extent of this effort. The research on ALD approach is of particular interest, since the Si industry is getting familiar with ALD Hf-based dielectrics and this approach has the potential to become a manufacturable technology.

Using In-rich InGaAs as surface channel, high-performance inversion-mode high-k/III-V NMOSFETs have been demonstrated. By further improving on-state performance, such as maximum drain current I_dss and peak transconductance G_m, the off-state performance or subthreshold characteristics need to be seriously evaluated for digital applications. In this talk, we review some new progresses on deep-submicron inversion-mode In_0.7Ga_0.3As NMOSFETs using 2.5 nm-5.0 nm ALD Al₂O₃ as high-k gate dielectrics. The G_m exceeds 1.1-1.3 mS/µm and starts to approach the values from InGaAs HEMTs. The scaling metrics, such as threshold voltage (V_T), I_on/I_off ratio, sub-threshold swing (S.S.), the drain induced barrier lowing (DIBL), as a function of the gate length from 150 nm to 250 nm are systematically studied. Retro-grade structure and halo-implantation are also applied to III-V MOSFET field to improve the off-state performance of InGaAs MOSFETs.In order to achieve better gate control capability, new structure design like FinFET demonstrated successfully in Si devices, is strongly needed for short-channel III-V MOSFETs. However, unlike Si, the dry etching of III-V semiconductor surface has been believed to be difficult and uncontrollable, especially related with surface damage and integration with high-k dielectrics. We also review some results on the first experimental demonstration of inversion-mode In_0.53Ga_0.37As tri-gate FinFET using damage-free etching and ALD Al₂O₃ as gate dielectric. The SCE is greatly suppressed.

The work is in close collaborations with Y.Q. Wu, Y. Xuan, J.J. Gu and M. Xu. We also would like to thank valuable discussions with D. Antoniadis, M.S. Lundstrom, R.M. Wallace, K.K. Ng, M. Hong, and J. Woodall.

Identification of the source of interfacial defects between high-k films and III-V substrates is crucial for developing passivation methods. Efforts have been made to isolate defects based on a specific chemical moiety at an interface. A study reported that doubly-O coordinated Ga and displaced As formed when GaAs is exposed to oxygen, induces mid-gap states¹. Another study suggested that high activity interface defects originate from structural disorder instead of specific chemical moieties². This project aims to understand the nature of Al₂O₃/InGaAs interface defects by relating composition to electrical performance. The modification of InGaAs(100) surfaces due to surface cleaning, Al₂O₃ deposition, and post deposition annealing (PDA) was investigated using capacitance-voltage (CV) curves, large AC signal conductance (LSC), and x-ray photoelectron spectroscopy (XPS). Al₂O₃ films were deposited by atomic layer deposition (ALD) using trimethylaluminum (TMA) and water precursors on native oxide covered and aqueous HF etched InGaAs(100) surfaces. XPS analysis on a native oxide sample revealed ~8Å oxide (52% As, 29% Ga, and 21% In) and a monolayer excess of As on an As-terminated substrate. TMA reacted on this surface during ALD, thinning the oxide to ~4.2 Å (45% As, 29% Ga, and 27% In). Aqueous HF treatment removed the native oxide and produced an As-rich surface, which re-oxidized in air. Surfaces consisted of ~4.2 Å oxide (91% As) and 1.5 monolayer excess As on an As-terminated surface. ALD Al₂O₃ on the liquid-cleaned surface produced a chemically sharp Al₂O₃/InGaAs interface with less than a monolayer of As oxide. CV and LSC measurements were performed on Au/Ni/10 nm Al₂O₃/InGaAs stacks. The deep-level surface recombination velocity (SRV) values extracted represent the net effect of interface defects, which includes the defect density and capture cross section. The similar SRV values obtained for native oxide (34+6 cm/s) and aqueous HF (29+13 cm/s) prepared surfaces suggest that the presence or absence of oxides was not the only determining factor. PDA in forming gas and NH₃ ambients significantly improved the electrical quality, as reflected in SRV values of 1 to 5 cm/s for both surfaces. XPS analysis showed increased excess As and Ga₂O₃ at the interface of both surfaces, likely due to thermally or H-induced reactions between interfacial As oxide and Ga atoms in the substrate. These results suggest that high activity defects in III-V’s could be associated with interfacial dangling bonds and are amenable to standard passivation methods used in Si technology.

¹Hale M. J. et al, J. Chem. Phys. 119(13), 2003

²Caymax M. et al, Microelectron. Eng. 86, 2009

Compound (III-V) semiconductors are currently being investigated to replace Si as channel material in metal oxide semiconductor field effect transistors. A significant challenge is the high trap density (D_it) at the dielectric/III-V semiconductor interface, causing Fermi level pinning. Recently, it has been reported that the D_it can be reduced by sulfur passivation and hydrogen annealing for Al₂O₃/In_0.53Ga_0.47As interfaces.

In this presentation, we will present our studies of the effect of forming gas anneals on the electrical properties of HfO₂/In_0.53Ga_0.47As metal oxide semiconductor capacitors . HfO₂ films with thicknesses between 9 and 18 nm were deposited in-situ on As-decapped n-type In_0.53Ga_0.47As channels by chemical beam deposition using hafnium tert-butoxide (HTB) as the source. Samples were post-deposition annealed in forming gas. For comparison samples annealed in nitrogen were also studied. Capacitance-voltage (CV) and conductance-voltage (GV) curves were measured at room temperature. The interface trap density D_it was quantified using both the Terman and the conductance methods. The conductance method showed that the D_it was reduced from 1.3Χ10¹³cm^-2eV^-1 to 8Χ10¹²cm^-2eV^-1 near midgap. The conductance peak shifted in frequency with a change in negative gate voltage, consistent with an unpinned Fermi level. The 1 MHz CV curve reached the calculated minimum capacitance value, indicating Fermi level unpinning. The nitrogen annealed control sample did not reach the minimum capacitance and the conductance peak shift at negative bias was moderate, indicating Fermi level pinning at midgap. We will also present comparisons of the extracted band bending for both nitrogen and forming gas annealed stacks and discuss the mechanisms by which forming gas anneals can reduce the midgap D_it.

CMOS scaling is at the heart of the microelectronics revolution. The ability of Si CMOS to continue to scale down transistor size while delivering enhanced performance is becoming increasingly difficult with every generation of technology. For Moore’s law to reach beyond the limits of Si, a new channel material with a high carrier velocity is required. A promising family of materials for this is III-V compound semiconductors.

III-Vs are well known for their unique suitability for high frequency electronics. III-V-based integrated circuits are currently in use in a variety of communications and defense applications. The prospect of III-Vs entering the logic roadmap is tantalizing. This work reviews some of the critical issues.

The barrier for insertion of a new channel material into the CMOS roadmap is huge. Any new technology has to beat Si designs in performance at device footprints that allow the integration of billions of transistors on the same chip. In addition, cost-effective manufacturing must be realized.

To make this work, a III-V CMOS technology has to solve a number of challenging technical problems. The development of a gate stack that includes a high-K dielectric and yields a high-quality semiconductor interface with a III-V compound semiconductor is up there as one of the greatest and most fascinating problems in modern semiconductor technology. Recent research suggests that this is an eminently attainable goal. Transistor size scalability is also a major worry. Will it be possible to scale future III-V transistors to the required dimensions while preventing excessive short-channel effects and attaining the demanding parasitic resistance objective? This is a topic that will call for extensive experimental and simulation research. Fortunately, calibrated simulators today reproduce quite well the characteristics of 30 nm gate length III-V FETs and should be valuable in projecting to devices in the 10 nm range. If planar device designs are unsuitable, 3D designs might offer a viable path. Recent 3D device demonstrations with impressive characteristics give hope that this is a promising strategy. A future III-V CMOS technology will also have to “look and feel” as much as Si as possible. This calls for the formation of thin high-quality III-V layers on top of large Si wafers. In fact, depending on what emerges as the best option for the p-channel device, a major challenge in itself, two dissimilar materials might need to be integrated side by side in very close proximity on top of a Si wafer. These are all great problems that will require the coordinated attention of scientists and technologists with expertise in many different domains.