With the fundamental limits to the aggressive device scaling in Si CMOS technology, there is significant ongoing research exploring alternate channel materials such as III-V and Ge. These materials hold promise to produce more power efficient transistors compared to current silicon technology. Due to their high carrier mobility, compound III-V semiconductors such as InGaAs and InSb, are being investigated in surface as well as buried channel devices where the inversion or majority carriers determine the device characteristics, respectively. The success of III-V in potential CMOS technology depend on heterogeneous integration on silicon with thinner buffer layers; compatible, low leakage and thermally stable gate dielectric with low interface state density; as well as defect free junctions with low external or access resistance. In addition it is key to develop, standardize and orient various physical and electrical characterization techniques to probe and evaluate the interface and bulk characteristics effectively and correctly at the atomic level. Significant amount of promising research is being done in these modules and there still remain several opportunities to reduce parasitic contributions.

The integration of high-k dielectrics with high mobility III-V semiconductors is important due to the need for higher speed and lower power electronic devices than are offered by Si-based technologies. While high-k dielectric deposition on GaAs and InGaAs semiconductors appears particularly promising, the removal of native oxides and the growth an ideal dielectric layer remains a serious challenge. This obstacle arises in part from the high density of defects present at most GaAs-dielectric interfaces, and is related to Fermi-level pinning at the interface. Several groups have shown that chemical cleaning and subsequent passivation of the interface prior to dielectric deposition can greatly reduce the interface state density (D_it). However, few passivation solutions are practical for future large scale CMOS device manufacturing.

Although several studies (including our own) have shown the reduction of native oxides on GaAs and InGaAs during atomic layer deposition (ALD) of dielectrics, detailed structural and chemical information about the interface and reduction process have not been reported. We have examined depth profiles of the elements in native oxides and ALD-deposited Al₂O₃ layers on GaAs substrates with an integrated tool that enables ALD growth with in situ characterization by medium energy ion scattering spectroscopy (MEIS). Films were also analyzed by x-ray photoelectron spectroscopy (XPS).

We will present data on the reduction of surface “native” oxides from GaAs substrates following reactions with trimethylaluminum (TMA) precursor. MEIS and XPS measurements after one single TMA pulse without oxygen exposure show that ~65% of the native oxide including ~75% of the As oxides are reduced, and a 5Å oxygen rich aluminum oxide layer is formed. XPS also shows that 3 additional TMA pulses reduce all As oxides to a level below our detection limit, and the Ga oxides were also reduced substantially. Further MEIS study of Al₂O₃ grown with the normal atomic layer deposition cycles of TMA and water shows that the growth rate of Al oxide during the reduction of native oxides is faster than the rate after the reduction. The preferential interface reduction of native oxides (especially AsO) helps create a higher capacitance, lower interface defect density CMOS gate stack.

The ideas of using high-κ dielectrics as gate oxide and high mobility semiconductor as channel material are promising means of prolonging the scaling of CMOS technology to post Silicon era. However, it has been extremely challenging to produce a high quality oxide/channel interface that yields sufficient device performance for future CMOS. The unwanted chemical species such as residue native oxide, surface carbon, and hydro-carbon can result in defect states at the interface or inside dielectrics. These states can enhance carrier scattering and degrade device threshold voltage. Several recent studies, including ours, showed that, above certain temperature, volatile metal-organic precursors such as TMA can chemically react with the native oxides on the GaAs or InGaAs surface, result in effective removal of native oxide species, and chemically clean interface. This effective is known as the “self-cleaning” ALD growth. Previous studies are largely based on in situ XPS and MEIS measurements on ALD grown samples at various stages during the first few cycles. In this work, we will report on the effect of “self-cleaning” ALD growth and post ALD forming gas annealing on the electrical properties of metal/Al₂O₃/GaAs MOS capacitors. We found the combination of the two treatments can significantly enhance the device C-V characteristics. Our preliminary results showed that frequency dispersion of ~2% per decade in the accumulation capacitance and interface state density (D_it) of ~5x10¹² eV^-1 can be achieved. We also correlated the electrical result with XPS and MEIS studies of the ALD grown Al₂O₃ films and as well as electronic structure at Al₂O₃/GaAs interface. We will also report on the “self-cleaning” growth study of high-κ (Al₂O₃ and HfO₂) on Ge substrate and corresponding electrical result on MOS-CAPs.

This work was supported by the FCRP Focus Center on Materials, Structures and Devices and the Texas Enterprise Fund.

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2 nm thick films of HfO₂ have been deposited on Ge(001) substrates by remote plasma chemical vapor deposition for (i) multiple etching cycles in dilute HF followed by distilled water rinsing, and (ii) an in situ remote plasma-assisted nitridation (RPAN) process. In a second set of studies, the step(i) pre-clean was replaced by a basic re-clean using methanol and NH₄OH. Studies by X-ray absorption spectroscopy (XAS) in O and N K edge regimes, were used to monitor HfO₂ nano-grains morphologies. Previous studies indicated epitaxial textured HfO₂ and TiO₂ films were obtained on Ge(001) surfaces. However, these studies were based on a recipe that worked, and did provide insights to significant connections between pre-cleaning and post deposition annealing. We have found two aspects of processing are crucial, and these were evaluated spectroscopically. Electrically active defects in metal-oxide-semiconductor test devices indicated high-defect densities correlated directly with Ge and O reacting with HfO₂ in the interfacial transition region, resulting in mixed-morphology grains.

Interfacial and bulk film degradation are also detected in XAS O K edge measurements. The occurrence of a monoclinic (m-)HfO₂ E_g edge structure is associated with Ge-O free interfacial transition regions. Ge-O interfaces results in tetragonal (t-)HfO₂, or mixtures of t-HfO₂ and m-HfO₂ grains. Acidic and basic pre-cleans each followed by an RPAN process prevented reactions between Ge-O surface bonding and plasma-excited HfO₂ precursors, consistent with textured m-HfO₂ films. Spectroscopic ellipsometry indicated that Ge-O bonding was significantly higher for acidic pre-cleans compared with basic pre-cleans. Post deposition annealing cycles with textured m-HfO₂ films were consistent with this difference. Two step annealing after the acidic clean, the first at 550°C in Ar, and the second at 800°C in Ar, resulted in textured m-HfO₂ directly in contact with a reconstructed Ge(001) surface. N K edge XAS, had previously indicated complete release of N after annealing to 700°C in Ar. In contrast, with less Ge-O interfacial bonding in the basic pre-clean, Ge-O and Ge-N interfacial bonds were eliminated sequentially during an 800°C anneal in Ar. O K edge XAS for HfO₂ with the X-ray polarization in the direction of the dimer rows of Ge(001) wafers, or perpendicular to that direction indicated similar textured growth. This is consistent with the textured m-HfO₂ films having nano-grains aligned at ±45^o relative the dimer row direction.