AVS2004 Session MS-ThM: Advanced Process Control

Thursday, November 18, 2004 8:40 AM in 303B

Thursday Morning

Time Period ThM Sessions | Abstract Timeline | Topic MS Sessions | Time Periods | Topics | AVS2004 Schedule

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8:40 AM MS-ThM-2 Fault Detection and Classification Using RGA in Semiconductor Manufacturing
Y. Xu, J. Byrne, H. Clark, J. Parker (IBM); J. Blessing (MKS)
A new advanced residual gas analysis (RGA) system was jointly developed by IBM and MKS-Spectra and implemented in IBM's 300-mm wafer fabrication facility for the purpose of process monitoring and fault detection. The RGA system was integrated into the Computer Integrated Manufacturing (CIM) architecture using IBM's Advanced Process Control (APC) third party interface, an Extensible Markup Language (XML) based messaging system. The APC third party interface presents a brand new APC/sensor integration methodology allowing the RGA application (or any other sensor for this matter) to have access to both tool level event/trace/recipe data and fab level process/wafer information. A centralized database is used to manage the RGA system and to store summarized RGA data. Several examples will be offered to demonstrate how the role of the RGA system has expanded far beyond traditional photoresist detection and tool vacuum integrity. Its ability to quickly detect the undesirable process variations and incoming contaminations (photoresist or non-photoresist) proves to be critical to improving product yield, tool availability and ultimately the profitability of the fab. RGA fault classification is another important topic that will be covered. This classification is required to facilitate the proper handling of various RGA faults. One approach under consideration is to apply multi-variable analysis techniques to RGA data analysis. Some preliminary results will be given in the discussion.
9:00 AM MS-ThM-3 Using Process Control to Address Manufacturing Challenges at 300mm
T.J. Sonderman, C. Bode (AMD)
The implementation of fully automated fab technologies will help ease the transition to 300mm manufacturing by making the most of the 300mm toolset capabilities. The transition to 300mm necessitates a level of process control improvement commensurate with the increase in the intrinsic value of the processed wafers. The key will be to keep these costs low while maximizing the value of each wafer. Part of the solution lies in establishing a fully automated system that allows for maximum predictability of output with manufacturing capabilities such as Advanced Process Control (APC). APC, a part of AMD’s Automated Precision Manufacturing (APM) technology, will be one of the key manufacturing technology that supports the transition. APC capabilities will need to evolve past lot-to-lot control to wafer-to-wafer control. 300mm tools will need to consider wafer-to-wafer control and extend the ability to change the process recipe for each individual wafer, in an automated fashion, as required. In addition, the control of individual processes will need to be integrated into a more holistic approach. This presentation will explore the evolution from unit process control to fab-wide automation. A holistic approach for factory automation goes beyond the optimization of performance within a given process or batch of wafers to focus on optimizing the output of the entire factory. The systems enabling optimization of process control are developed in coordination with advanced systems for automated yield analysis and production control. This integrated approach allows for a process control system that is both more flexible and more precise. Thomas Sonderman will discuss the manufacturing challenges that organizations face within 300mm and the benefits afforded to the market by moving to full automation. His presentation will draw on years of experience in the integration of these technologies to describe the essentials of a highly-automated 300mm manufacturing facility.
9:40 AM MS-ThM-5 Run-to-Run Process Control And Equipment Monitoring for Advanced Etch Applications.
J. Yamartino, D. Mui, H. Sasano, W. Liu, M. Shen, J.P. Holland, V. Todorow, A.M. Paterson (Applied Materials, Inc.)
Run-to-run process control provides a means for significantly improving the process capability index of a process tool as well reducing cycle time of product wafers. The Applied Centura Transforma Etch system provides the capability for controlling and reducing wafer-to-wafer CD variations for critical etch processes including gate etch. These capabilities includes the ability to adjust multiple process parameters based on multiple inputs from either the Fab Host or integrated CD metrology for both feedforward and feedback applications. In addition, an analysis of etch chamber data from several Applied Materials Etch systems demonstrates the importance of monitoring the chamber data for stability and excursion control. A model of the chamber behavior is created using a multivariate analysis of chamber data taken under known good production conditions. This model is then used as a baseline to which subsequent runs are compared. Excursions are detected using an overall health index and classified in terms of the chamber variable or variables responsible for the excursion. The run-to-run monitoring functionality provides a powerful means for maintaining equipment uptime and reducing wafer scrap. Finally, run-to-run monitoring of chambers which are under feedforward/feedback control enhances the capabilities of advanced process control. Examples from production data demonstrate the important link between monitoring and control.
10:00 AM MS-ThM-6 Gate Sidewall Profile Control for Plasma Etch Tool
J. Tanaka (Hitachi Ltd., Japan); A. Kagoshima, D. Shiraishi, H. Yamamoto, S. Ikuhara, M. Yoshigai (Hitachi High Technologies Corporation, Japan)
The scale of semiconductor devices has been shrinking year by year. Plasma etch tools have to meet demands for the tight control of gate critical dimensions (CD) for complementary metal oxide silicon (CMOS) devices. Although the hardware of plasma etch tools has been modified to stabilize the gate CD after the etch process, there remains slight wafer-to-wafer drift of the gate CD caused by the changing wall surface conditions. Run-to-run feedback control of the etch process is beginning to be used to eliminate the residual gate CD drift. To eliminate the gate CD drift by run-to-run control, we controlled the oxygen flow rate. Then we found the gate CD could not be controlled without changing the gate sidewall profile. To monitor the gate sidewall profile we used a CD scanning electron microscope (CDSEM). The CDSEM can measure a line width from the intensity profile of secondary electron. Thus it is natural that we should expect the intensity profile measured by the CDSEM to have a strong correlation with gate profile. We found the change in the gate sidewall profile can be monitored using the intensity profile of CDSEM. The etch process used for the experiment consists of four steps: a breakthrough step, a main etch step 1 (ME1), a main etch step 2 (ME2), and an over etch step. In our first trial experiment we controlled oxygen flow rate in ME2. Although the gate CD changed as expected, the gate sidewall was tapered to degrade its vertical shape. Thus we moved the control step to ME1. When we changed the oxygen flow rate in ME1, we could control the gate CD without changing the gate sidewall profile. Finally a gate CD drift in a lot was suppressed keeping the same gate sidewall profile.
10:20 AM MS-ThM-7 DRAM Gate CD Control in Dry Etch Process using Optical Integrated Metrology
Y.J. Jung, Y.J. Kim, G.J. Min, C.J. Kang, H.K. Cho, J.-T. Moon (Samsung Electronics Co., LTD., Korea); J.W. Shon (Lam Research Corporation)
In current CMOS technology, a traditional sequence to obtain a target post etch CD is to perform lithography patterning and measure the CD in resist followed by dry etch and strip process. There is a specification for the CD in resist, which may result in target post etch CD. After the measurement of the CD in resist by using in-line scanning electron microscope (SEM), it is determined whether the rework process of lithography is necessary or not to meet the specification of the CD in resist. This kind of traditional CD control sequence, however, may be a source of following problems. First, since the measurement of the CD in resist cannot be performed for every lot as well as every single wafer due to throughput in mass production environment, it is not sure that all lots and/or wafers meet the specification of the CD in resist. Second, rework process for out of specification requires additional time, resources, and cost, which result in the decrease of productivity. Third, the measurement of the CD in resist using SEM causes CD slimming, which may give uncertainty error in CD determination. Although CD control in dry etch process using the optical integrated metrology is one of the promising candidates to overcome the above problems, it has not been applied in the DRAM Gate etch process due to the difficulty in thick Si@sub 3@N@sub 4@ hard mask. In this work, DRAM gate CD control in dry etch process is applied to sub-100 nm transistor fabrication. Gate etch of Si@sub 3@N@sub 4@ hard mask is performed using dual-frequency capacitively coupled plasma (DF-CCP) type etcher. After the CD in resist for each wafer is measured using the optical integrated metrology, the process controller determines a proper process condition to meet the target post etch CD according to the predetermined model of CD control with the measured CD in resist. Throughout this CD control in DRAM gate etch process, the variation of CD in resist (@>=@10nm) is reduced dramatically (@<=@2nm).
10:40 AM MS-ThM-8 Improving Etch Process Control with Advances in Vacuum Measurement
J. Sipka, S. Pewsey, D. Leet (Mykrolis Corporation)
As each successive technology node is developed, staying the course of 'Moore's Law' has required device size scaling, and often, new materials development as well as tighter manufacturing process control, adherence to specifications and improved, tighter tolerances for chamber level devices. Process pressure repeatability at low mTorr setpoints is critical in obtaining the desired yields in Etch Processes. The process chamber pressure control system is a key component in achieving the process repeatability. At the heart of the chamber pressure control system is the Capacitance Diaphragm Gauge (CDG). If the fundamental vacuum measurement shifts or varies over time, the chamber pressure control sub-system will track this, resulting in changes in etch rate resulting in wafer lot to lot variability. A study was conducted to correlate (Etch) Process CD data with the (zero) stability of a new generation of Digital Process Vacuum Gauges. This paper will show test results of long term zero stability, process repeatability, and environmental sensitivity of a low-pressure heated digital capacitance diaphragm gauge under typical Semiconductor Etch conditions and under controlled test conditions. This paper will also address the causes of zero output shifts on Capacitance Diaphragm Gauges and design techniques utilized to minimize this effect.
11:00 AM MS-ThM-9 New Intelligent Molecular Flow Sensor-Experimental Definition of Flow Properties
H.S. Sagi (ATC, Inc.)
A new Intelligent Molecular Flow Sensor (IMFS) enables, for the first time, direct gas flow measurements in the transitional and molecular flow regimes, as well as in the slip and continuum flow regimes, thereby enabling flow measurements at pressures ranging from vacuum through atmospheric. The properties of this sensor are investigated, along with the sensor's transitional operating ranges. The IMFS operates as a mass flow sensor (directly measures the mass flow) in the transitional and molecular flow regimes, and it operates as a volumetric flow sensor in the continuum and slip flow regimes. Understanding of these properties and ranges of operation are critical for demanding leak testing, sealed closure integrity testing and vacuum test applications.
Time Period ThM Sessions | Abstract Timeline | Topic MS Sessions | Time Periods | Topics | AVS2004 Schedule