AVS2004 Session PS2-TuM: New Gate Conductor Etching

Tuesday, November 16, 2004 8:20 AM in Room 213B

Tuesday Morning

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8:20 AM		PS2-TuM-1 Study of Refractory Metal Nitrides/HfO₂ Gate Stack Etching Using Inductively Coupled Plasma J.H. Chen, W.S. Hwang, W.J. Yoo, S.H.D. Chan (National University of Singapore, Singapore); D.-L. Kwong (University of Texas, Austin) Metal gates/high-K gate stacks are expected to be used for 45nm and beyond MOSFETs, replacing conventional Poly-Si/SiON gate stacks. Refractory metal nitrides (RMNs) including TaN, TiN, and HfN are being studied extensively as the promising candidates for future metal gates, because of good thermal stabilities, and suitable work functions on hafnium based high-K dielectric for CMOS devices. In this work, we investigated the etching properties of RMNs (TaN, TiN and HfN) on HfO₂ using inductive coupled plasma (ICP) of HBr/Cl₂/O₂. Results show that the etch rate of ~2800Å/min for TaN, ~2500Å/min for TiN and ~4000Å/min for HfN can be achieved at 10mTorr in HBr/Cl₂ plasma (inductive power of 400W and DC bias of 144V). Etch rates of RMNs increase rapidly with increasing ion density and energy. The dependences of etch rates of TaN, TiN and HfN on ICP parameters are different, but all are more sensitive than that of poly-Si. Etch electivity of RMNs with respect to HfO₂ was lower, comparing to poly-Si/SiO₂ gate stack structure. Adding small amount of O₂ into Cl₂ or HBr plasma enhanced the etch selectivity of RMNs with respect to HfO₂, because it can suppress the etch rate of HfO₂, without a significant change the etch rates of RMNs. Improvement of etch selectivity can be also achieved by reducing ion energy and increasing pressure. Very anisotropic profile of these three RMNs metal gates can be acquired by reducing pressure, increasing ion energy and adding more Cl₂ in the gas mixture. Optical emissions at 400-800nm wavelength were observed from RMNs etch byproducts in Cl₂ or HBr plasma, providing sharp etch end point signal. X-ray photoelectron spectroscopy analysis of etched surfaces shows that most of etch byproducts of these three RMNs etched by Cl₂ or HBr plasma are volatile at 10mTorr and 100°C, and residues are found to be mainly bromides and chlorides.
8:40 AM		PS2-TuM-2 Line Width Roughness Reduction for Advanced Metal Gate Etch and STI Etch with 193nm Lithography in a Silicon Decoupled Plasma Source Etcher (DPSII) T. Chowdhury, H. Lee, A. Renaldo, K. Ikeuchi, A. Habbermas, B. Bruggermann (Cypress Semiconductor); Y. Du, M. Shen, S. Deshmukh, J. Choi (Applied Materials, Inc.) 193nm lithography has become necessary as the critical dimensions of semiconductor devices continue to scale down towards sub 90 nm dimension. From a device point of view the effects of higher Line Edge Roughness (LER)/Line Width Roughness (LWR) are studied. Metrology aspects of LER/LWR are also included in the study. From dry etching perspective, however, 193nm resist brings new challenges due to its poorer plasma etch resistance, LER/LWR and lower thickness compared to 248nm DUV resist. This paper presents a successful development of advanced 0.1µm metal gate and STI etch application using 193nm lithography on Applied Materials' decoupled plasma etcher DPSII system. Process chemistry and process parameters for nitride mask step were thoroughly explored and investigated vs LWR. Post-etch measurement of line width roughness shows an average of 6nm LWR. It was observed LWR is a strong function of etch chemistry (CHF3/CF4 based HM open vs CH2F2 based HM Open), reaction regime (15 mT vs 30 mT) and ICP vs MERIE etc. A detailed study showing methods to reduce LWR is presented in this paper. .
9:00 AM		PS2-TuM-3 Plasma Etching of Metal/High-K Gate Stack A. Le Gouil (STMicroelectronics, France); T. Chevolleau, G. Cunge, L. Vallier, O. Joubert (LTM-CNRS, France); P. Mangiagalli, T. Lill (Applied Materials) The rapid downscaling of metal-oxide-semiconductor transistors imposes new materials for the gate stack. Metal gate electrode receives more attention than conventional poly-Si gate electrode when high permittivity material is used as the gate dielectric. In addition to the introduction of these new materials, critical dimension control of less than 3nm must be achieved for the 45 nm technological node. In this work the metal gate etching process is developed with a poly-Si/TiN stack for the gate electrode and HfO₂ (3.5 nm thick) as the gate dielectric. Anisotropic and selective etching of the gate stack requires the development of a multi-step etching process. First, the silicon part of the gate is etched using an HBr/Cl₂/HeO₂-based chemistry. We have then studied several chemistries (Cl₂ , HBr and their mixture) to etch the TiN layer anisotropically and selectively with respect to HfO₂. The selectivity and surface modification of the HfO₂ layer after exposition to the plasmas have been studied by X-ray Photoelectron Spectroscopy and AFM. While highly anisotropic etching can be observed in pure Cl₂ plasmas, a very rough HfO₂ surface is observed in this case, partially due to the presence of TiO_x residues on the HfO₂ surface. In addition the selectivity toward HfO₂ is poor. By contrast HBr provides a higher selectivity with less roughness. Hence using a mixture of HBr/Cl₂ appears to be the best strategy to achieve both anisotropic and selective etching of TiN film over HfO₂. Finally, a complete metal gate process requires HfO₂ removal after the gate definition. We will show that this high temperature plasma process can seriously damage the gate profile due to the lack of passivation layer on the TiN sidewalls (undercutting is observed). This suggests that a protection layer must be formed after or during TiN etching in order to protect the metal gate before removal of the dielectric of the gate.
9:20 AM		PS2-TuM-4 Etching Ruthenium with O2- and Cl2-Containing Inductively Coupled Plasma C.-C. Hsu, D.B. Graves, J.W. Coburn (University of California, Berkeley) Ruthenium (Ru) plasma etching has been studied using inductively coupled plasma (ICP) with O2- and Cl2-containing plasma, with the objective of understanding the relationship between plasma characteristics and the competition between wall deposition of etch by-products and the creation of volatile etch by-products that flow into the downstream. The ICP was characterized by in-situ ion and neutral mass spectrometers, a chamber wall-mounted quartz crystal microbalance, optical emission spectroscopy, a wall-mounted ion flux probe, and an FTIR spectrometer in the turbomolecular pump foreline. Ru films were etched from 150 mm diameter wafers placed on a rf-biased substrate. Ru can be etched readily by Ar and O2-containing plasma. Cl2 addition results in significant changes in etch rate, wall deposition behavior, and downstream etch product composition. With 10 sccm Ar and 10 sccm O2 at 10mT pressure and 100V bias voltage, a 60 angstroms/min etching rate was observed. In addition, without Cl2 addition, no RuO4 was observed in the foreline, and almost all etch by-products were deposited on the chamber wall. With Cl2 addition (Ar/O2/Cl2 plasma), the etching rate increased by a factor of 5, RuO4 was observed downstream by FTIR, and virtually zero wall deposition rate was observed. One interpretation of the observations is that chlorine addition to the Ar/O2 plasma results in a more volatile Ru-oxychloride etch product, increasing both film etch rate and chamber wall re-etch rate.
9:40 AM		PS2-TuM-5 Ru Etching Characteristics in Capacitively Coupled Ar/Cl₂/O₂ Plasma S. Rauf, P.L.G. Ventzek, V. Vartanian, B. Goolsby (Freescale Semiconductor); S. Burnett (International Sematech); L. Chen (Tokyo Electron America Inc.) As the semiconductor industry attempts to replace the traditional gate dielectric, SiO₂, with higher-κ dielectrics (e.g., HfO₂), a thin metal layer need to be introduced in-between poly-silicon and gate dielectric to control conductor-dielectric interface properties. Ru is one metal that is being considered for this application. Along with electrical characteristics, the metal etching properties and compatibility of metal etch chemistry with other materials will determine how suitable a particular metal is for use in transistor gates. This paper describes a combined experimental and computational modeling investigation of Ru etching characteristics in a commercial dual frequency capacitively coupled Ar/Cl₂/O₂ plasma. Experiments explored the impact of gas mixture, RF power, gas pressure, and wafer temperature on Ru etch rate. Fourier transform infrared spectroscopy was also used to analyze effluents downstream from the plasma. Computational modeling was done using Io, a 2-dimensional plasma equipment simulation code. Plasma modeling results and blanket wafer etch rates were used to put together the Ru etch mechanism. Results indicate that reactive ion etching is the dominant Ru etch process, where O is first absorbed on Ru surface (generating RuO_x) and the resulting compound is sputtered by energetic ions. The model captures experimental etch rate trends well at low gas pressures, but there is disparity between model and experiment at higher pressures. This difference is likely due to thermalization of sputtered Ru and RuO_x in the plasma, whose plasma chemistry is not well understood and, therefore, not accurately captured in our plasma chemical mechanism.
10:00 AM		PS2-TuM-6 An Isotropic SiGe Etch Process for Fabrication of Silicon-on-Nothing Transistors T. Sparks, S. Rauf (Freescale Semiconductor, France); G. Cunge, L. Vallier (LTM-CNRS, France) As the device dimensions are shrinking, the development of new transistor structures is essential to meet the ITRS roadmap device performance specifications. One such device, the Si-on-nothing (SON) transistor, utilizes a sacrificial SiGe epitaxial layer underneath a thin transistor active channel region. The SiGe layer is removed using a lateral isotropic etch process. Isotropic chemical downstream etch processes for SiGe removal suffer from high etch rates, low selectivity to Si and lack of insitu monitoring processes such as optical emission analysis. An alternative approach for lateral SiGe etching has been developed utilizing an inductively coupled plasma (ICP) operating in the 'remote' plasma mode, and it is described in this presentation. The etch process was designed using a combination of computational modeling and experiments. The Hybrid Plasma Equipment Model (HPEM) from the University of Illinois was utilized for plasma modeling and process design, and experiments in a commercial ICP reactor were used to confirm the predicted conditions. The plasma model was also coupled to a string-based feature scale model, where the etch mechanism was based on blanket wafer etching experiments and information available in literature. Etching was conducted in CF₄ containing plasmas, which will generate SiGe etchants (e.g., F) as well as polymer precursors for Si (e.g., CF₂). Possible mechanisms were investigated to understand the observed high isotropic etch selectivity of SiGe to Si. Process modeling also identified an intermediate gas pressure regime where plasma was localized close to the inductive coils away from the substrate. If the plasma is operated in this gas pressure regime without RF bias, ion energy flux at the substrate was small while flux of neutral etchants and polymer deposition precursors was reasonable. The resulting SiGe process therefore offered good selectivity to Si and a controllable etch rate.
10:20 AM		PS2-TuM-7 X-ray Photoelectron Spectroscopy Study on Walls Coatings and Passivation Layers Generated on Sidewalls Trenches during Shallow Trench Isolation Processes. C. Maurice, B. Pelissier, G. Cunge, O. Joubert (LTM-CNRS, France) For IC technology where delineating ever-finer structures is critical, wafer-to-wafer reproducibility is essential. Inherent to plasma processes, the coatings deposited on the reactor walls can disturb reproducibility by influencing the plasma chemistry. Simultaneously to walls coatings formation, passivation layers issued from etch products are deposited on the sidewalls of the etched patterns. These passivation layers, mandatory in obtaining controlled profiles are dependent on reactor walls conditions. This study proposes an XPS analysis of both walls coatings and of the passivation layers deposited during Shallow Trench Isolation (STI) processes. First, using a simple piece of Al₂O₃ floating on top of a 200 mm diameter wafer, walls conditions have been simulated and the chemical composition of the walls coatings analyzed quasi in-situ after each etching steps of the process. Secondly, using the combined effects of geometrical shadowing (allowing the screening of photoelectrons coming from the bottoms of the patterns) and of electrostatic charging, the chemical composition of the passivation layers formed on feature sidewalls has been determined. Results validate the technique even in the case of STI etching where the passivation layers are very thick. Comparison between the results obtained on the final walls coatings and passivation layers reveals in both cases the formation of SiOCl layers and thus the important correlation between the two deposits. Comparison between SiO₂ and Si₃N₄ hard masks is performed. The impact of CF₄ addition in typical Cl₂/O₂ chemistries is also investigated.
10:40 AM		PS2-TuM-8 The Control of Electrode Impedance, Gas-Injection and Wafer-Temperature Radial Profile and their Effects on Poly-Gate Etching Performance M.H. Hagihara, L.C. Chen, F.H. Higuchi, Y.T. Tsukamoto, K.I. Inazawa (TEL); T.T. Tatsumi, A.K. Kawashima (Sony) The etch rate and CD radial uniformity can be effectively optimized by controlling the radial profile of the inlet gas, the plasma parameters and the wafer temperature. A 2-zone ESC is used to control the wafer temperature radial profile. The ion energy and electron density (n_e) radial distribution are controlled by the wafer-electrode's VHF impedance. The variable impedance is achieved by a series LC circuit where a variable capacitor is used. SCCM POLY source-plasma is generated by 60MHz VHF power while the 13.56MHz wafer-bias accelerates the ions. The passage of the 60MHz electron towards the wafer-electrode and hence, the n_e radial profile, is strongly effected by the wafer-electrode's 60MHz impedance. In addition to the wafer-electrode's 13.56MHz bias power, the ion energy is also effected by its 60MHz impedance. The etcher is also equipped with a 2-zone gas showerhead providing radial distribution control of the neutral species. Etch data were taken for 4 poly-gate steps: fluorocarbon-based BARC etching, fluorocarbon TEOS hard mask open, fluorocarbon-based high-dope poly etching and HBr-based poly etching. A radial SW (Surface Wave) probe is used to measure the radial n_e directly above the wafer at various 60MHz impedance settings. Etch rate, XSEM profile and top-down CD uniformity are also recorded for various VHF impedance settings, 2-zone gas injection ratios and various 2-zone ESC temperature settings. Provision of these additional control knobs significantly improve the uniformity of the etch results.
11:00 AM		PS2-TuM-9 Process Diagnostics and Optimization in Plasma Etch Chambers Using In-Situ Temperature Metrology P. MacDonald (OnWafer Technologies, Inc.); B. Hatcher, J.P. Holland (Applied Materials, Inc.); M. Welch, M. Kruger (OnWafer Technologies, Inc.) Performance metrics in plasma etching are strongly affected by various interacting mechanisms including direct chemical reaction, reactive etching, deposition, and mask erosion. Some of these basic etch mechanisms are extremely sensitive to temperature. As a result, across-wafer temperature variations are a first order indicator of etching performance in advanced plasma etch reactors. This temperature variation is a combination of effects ranging from reactor design to individual recipe parameters. With wafer-level thermal data available, any of these factors can be modified to improve process performance. This paper establishes concrete methodologies for in-situ process optimization using a wireless sensor system. The sensor system provides the precision necessary to break the ITRS "brick-wall" of "measurement precision of wafer surface temperature,"¹ by combining in-situ plasma SensorWafers and an advanced diagnostic data processing suite. This paper offers multiple examples on advanced polysilicon processes that illustrate rapid, effective process optimization and ESC diagnostics. In the process optimization section, state-of-the-art polysilicon etch chambers are evaluated for critical process characteristics. The effectiveness of temporal/spatial temperature signatures as indicators of process performance is demonstrated. Wafer-level thermal data is correlated to actual device results to verify performance of the optimized process. In the ESC characterization segment, multiple leading-edge ESC designs are evaluated to ensure process transferability and performance. The effectiveness of temporal/spatial temperature signatures to quickly and easily evaluate ESC design iterations is demonstrated. These diagnostics save considerable time and effort over the current methods established for ESC fingerprinting. ¹ ITRS: 2003, Table 6, Key Sensor Technology Requirements.
11:20 AM		PS2-TuM-10 New Mthod to Analyse Chamber Walls Coating during Plasma Etch Processes O. Joubert, G. Cunge, B. Pelissier, C. Maurice, L. Vallier (LTM-CNRS, France) In today's etching processes for microelectronic application the shape of the etched feature must be controlled within 5 nm. This nanometer-scale linewidth control requires a perfect process repeatability. In high density plasmas operating at low pressure it is difficult to achieve due to the deposition of organic (or mineral) layers on the reactors walls during the process. This formation of this layer on the reactor walls modifies the surface loss probability and the concentrations of radicals involved in the etching process, leading to process instabilities. However, the chemical nature of these layers, their deposition mechanism and their influence on the plasma chemistry remains poorly understood. Recently, we have developed a new and very simple method based on the fact that a small piece of Al₂O₃ floating on top of a 200 mm diameter wafer during an etch process experiences the same exposition to the plasma than the chamber walls. We have then use quasi in situ XPS measurements to have access to the chemical nature of the layers formed on the floating Al₂O₃, i.e the chamber walls, during plasma etching processes. Using this technique, we can determine accurately the chemical nature of the layers coated on the reactor walls after various etching processes including silicon and metal (TiN) gate etching. We will demonstrate that the final nature of the chamber wall coatings is strongly influenced by the presence of resist on the wafer, nature of the layers composing the gate stack and chemistries used during the different steps of the process. We will then discuss the cleaning strategies that are commonly used after gate etching processes and their limitations.