AVS2002 Session MS-TuM: Beyond Planar CMOS: Manufacturing Issues

Tuesday, November 5, 2002 8:20 AM in C-109

Tuesday Morning

Time Period TuM Sessions | Abstract Timeline | Topic MS Sessions | Time Periods | Topics | AVS2002 Schedule

Start Invited? Item
8:20 AM MS-TuM-1 A Systems Approach to Microelectronics
J. Heath (University of California, Los Angeles)
In this talk I will present progress toward the fabrication of a molecular electronic computing machine, and I will discuss concepts related to machine architectures, including multiplexing and demultiplexing architectures for connecting the nano-dimensions of chemical assembly with the sub-micrometer dimensions of lithographic patterning. I will also discuss working devices and circuitry based on molecular mechanical switching complexes, as well as 3-terminal molecular electronic FETs for achieving gain. Finally, I will present patterning techniques for achieving bit densities in the range of 10@super 11@ to 10@super 12@bits/cm@super 2@.
9:00 AM MS-TuM-3 Integrated Circuit Technology Scaling: From Conventional CMOS to the Nanoscale Era
P. Zeitzoff (International SEMATECH)
Integrated Circuit (IC) scaling per Moore’s Law has been the cornerstone for IC industry growth for the last 35 years. Based on the projections in the International Technology Roadmap for Semiconductors (ITRS), we will examine the MOSFET scaling envisioned to sustain Moore’s law for the next 15 years, during which the current MOSFET physical gate length of about 65 nm is expected to be scaled to about 9 nm. Issues discussed include the scaling of MOSFET performance, leakage, and power dissipation, as well as key innovations to enable the scaling. These include the potential utilization of high-k gate dielectrics, metal gate electrodes, and innovative source/drain (S/D) techniques such as raised S/D. Also, in the later stages of the ITRS, non-conventional, non-planar CMOS devices such as ultra-thin-body, fully depleted, double-gate MOSFETs may be utilized to overcome the limitations of conventional planar bulk CMOS transistors when the physical gate length is scaled to 25 nm or less.
9:40 AM MS-TuM-5 Nanoelectronics - Feast or Famine?
J.A. Hutchby, V. Zhirnov, G. Bourianoff (Semiconductor Research Corporation)
Many concepts have been proposed to provide new means for information processing technologies as the industry standard CMOS MOSFET approaches its fundamental limits of scaling. Some concepts propose use of a particular nanotechnology to replicate the function of a silicon transistor albeit on a much smaller scale. Much of the known circuit and system architecture concepts may well be applicable in this new paradigm. Examples of this category include carbon nanotubes and molecular electronics. Other concepts(e.g. Quantum Computing and Quantum Cellular Automata) offer completely new paradigms for information processing, and will require new concepts and infrastructure to architect the desired systems functions. In this paper, the authors will discuss some of the more advanced candidates for new information processingparadigms and will show one concept for there possible relationship to silicon CMOS at the end of the current SIA Roadmap.
10:20 AM MS-TuM-7 Beyond Planar CMOS. A Reliability Perspective
J. Maiz (Intel)
The aggressive scaling of the semiconductor technology continues relentlessly in order to satisfy the performance roadmap expectations created by "Moore's Law". The scaling of the planar CMOS transistor has been central to achieving past performance gains and remains as the main approach to realize the performance roadmap for at least the next decade. Concerns have been raised however, about the extendibility of this "evolutionary" approach because of the many integration, power and reliability challenges posed by the required use of exotic materials and extreme dimensional reductions. A number of companies and research institutions are looking into possible alternatives ranging from dual gate and FINFET transistors which still look & feel like CMOS devices, to more speculative and exotic solutions including quantum devices, molecular & organic transistors, novel non-volatile memory schemes, and carbon nanotube devices. Limited information exists on the reliability of such devices. This paper will discuss some of the key learnings reported, as well as speculate over the likely failure modes & mechanisms present for the more exotic configurations based on the extensive learning accumulated on the present planar CMOS devices and associated materials.
11:00 AM MS-TuM-9 Fabrication of Double-Gate Field Effect Transistors at the Limit of Device Scaling
H.-S.P. Wong (IBM T.J. Watson Research Center)
As silicon CMOS devices scale into the nanometer regime, the material set and device structures employed by conventional field-effect transistors (FETs) are beginning to reach their limits. One way to extend the scaling of the FET towards smaller gate lengths (less than 20 nm) is to employ the double-gate device structure.@footnote 1@ While the concept and the device physics of the double-gate FET has been explored for many years,@footnote 2@ the fabrication of the double-gate FET remains difficult.@footnote 3@ Self-alignment of the two gates with respect to each other and to the source and drain doping regions present a very difficult fabrication challenge. In addition, the thin silicon channel thickness required (5 to 10 nm) becomes a key manufacturing challenge as well as a unique opportunity to study fundamental device physics. This paper will review the history and state-of-the-art in double-gate device development, including the planar,@footnote 4,5@ vertical(VRG),@footnote 6@ and FinFET@footnote 7,8@ device configurations. This paper will also review the device physics considerations which drive technology progress from SOI to the ultimate limit of FETs, highlighting the role that double-gate FETs will play in the future. @FootnoteText@@footnote 1@H.-S. P. Wong, D. Frank, P. Solomon, H.J. Wann, J. Welser, Nanoscale CMOS, Proceedings of the IEEE, p. 259, 2001. @footnote 2@T. Sekigawa et al., Calculated threshold voltage characteristics of an XMOS transistor having an additional bottom gate, Solid State Electronics, p. 827, 1984. @footnote 3@H.-S. P. Wong, Beyond the Conventional Transistor, IBM J. Research and Development, p. 133, 2002. @footnote 4@H.-S. P. Wong et al., International Electron Devices Meeting, p. 427, 1997. @footnote 5@K. Guarini et al., International Electron Devices Meeting, p. 425, 2001. @footnote 6@S.-H. Oh et al., International Electron Devices Meeting, p. 65, 2000. @footnote 7@Y. Choi et al., International Electron Devices Meeting, p. 421, 2001. @footnote 8@J. Kedzierski et al., International Electron Devices Meeting, p. 437, 2001.
Time Period TuM Sessions | Abstract Timeline | Topic MS Sessions | Time Periods | Topics | AVS2002 Schedule