AVS2001 Session DI-MoA: High K Dielectrics I

Monday, October 29, 2001 2:00 PM in Room 130

Monday Afternoon

Start	Invited?	Item
2:00 PM	Invited	DI-MoA-1 Epitaxial High-K Gate Oxides on Silicon: Impact on Future CMOS Z. Yu, R. Droopad, J. Ramdani, J. Curless, C. Overgaard, J. Finder, K. Eisenbeiser, J. Wang, W. Ooms (Motorola Labs); Y. Liang, S.A. Chambers (Pacific Northwest National Laboratory) One of the main problems facing the semiconductor industry is the scaling of the gate dielectric of silicon CMOS devices. Currently, SiO₂ gate oxide is being used, but it suffers from tunneling leakage current and reliability problems at thickness below 2 nm. Alternative high-k materials to replace SiO₂ need to be developed as soon as possible. Single crystal oxides such as SrTiO₃ (STO) with a simple structure and a much higher k are ideal candidates for future CMOS gate dielectrics. A physically thick high-k layer can behave electrically like a thin one, thereby eliminating the tunneling leakage problems experienced with <2 nm SiO₂. These oxides also exhibit ferroelectric behavior and their use as the gate dielectric on Si can be exploited in the realization of a single transistor memory element. In this presentation, we will review the atomic simulation, MBE growth, structural, electrical and interface properties of high quality single crystal STO layers on Si with low leakage current density and effective oxide thickness (EOT) < 1 nm. The STO layers are characterized using RHEED, SE, XRD, AFM, TEM and XPS. Atomic simulations have been extensively carried out to predict the reliability of the structure of the epi-oxide/Si interface. The oxide films on Si(001) are (001) orientated as determined by XRD and pole figure analysis confirms that the perovskite oxide lattice is rotated 45° with respect to the Si lattice. AFM measurements shows rms roughness as low as 1.2 Å. Cross-sectional TEM shows smooth interfaces and dislocation free STO films. XPS has been used to determine the band offsets at the oxide/Si interface. Electrical measurements on MOS capacitors fabricated on wafer using platinum gate electrodes demonstrated leakage as low as 10^-8 A/cm² with interface state densities in the low 10^-11 cm^-2eV^-1. Results on MOSFET devices fabricated using STO as the gate insulator will be presented.
2:40 PM		DI-MoA-3 High Dielectric Constant Material as an Alternative Gate Dielectric in MOSCAP and MOSFET Applications Y.S. Lin, J.P. Chang (University of California, Los Angeles) ZrO₂ is investigated in this study to replace SiO₂ as the gate dielectric material in metal-oxide-semiconductor devices. ZrO₂ films were deposited on P-type Si (100) wafers by a rapid thermal chemical vapor deposition process using Zr(OC₄H₉)₄ as the precursor and oxygen as the oxidant. The two chemistries were introduced sequentially into the reactor with purging and evacuation in between. The deposited films were stoichiometric, uniform and extremely smooth based on X-ray photoemission, ellipsometry, and atomic force microscopy measurements. The high-resolution transmission electron micrograph showed a polycrystalline ZrO₂ film (monoclinic) and an interfacial amorphous ZrSi_xO_y layer on the silicon substrate. This interfacial layer is confirmed to be zirconium silicate based on the thermodynamic calculation, chemical etching resistance, and medium energy ion scattering analysis. Excellent step coverage was observed by depositing ZrO₂ over 300 nm features with an aspect ratio of 4. The conformal deposition profile can be simulated by the Monte Carlo method with a sticking coefficient on the order of 10^-4. In-situ transmission infrared analysis is used to examine the chemically absorbed surface species during the deposition process with various chemical exposures. Isotope labeling of oxygen is underway to assess the effect of the oxidation/annealing processes on film composition and electrical performance. The dielectric constant of RT-CVD ZrO₂ was 15-18, and the capacitance-voltage measurement showed a hysteresis around 100 mV, which was slightly higher than desired <45 mV value. The interface state density was ~ 1.2x10¹¹ cm^-2eV^-1, as determined by capacitance measure at various frequencies. NMOS transistors are made with n⁺ polysilicon gate, and good turn-on characteristic and low leakage current density of 2x10^-7 A/cm² at - 1.5V were observed.
3:00 PM		DI-MoA-4 High Frequency Characterization of Thin Films with High Dielectric Constant J. Westlinder, K. Larsson, H.-O. Blom, J. Olsson (Uppsala University, Sweden) New dielectric materials are required in future IC's. Not only a new gate oxide with higher dielectric constant is needed, but also high dielectric materials must be used in on-chip integrated capacitors in order to increase the integration density. We have investigated the high frequency behavior of (Metal-Insulator-Metal) MIM-capacitors in the frequency range from 1 MHz to 10 GHz. The insulator thin films (about 100 Å to 2000 Å) have been made of high dielectric constant materials, e.g. Ta₂O₅, ZrO₂, or HfO₂. In the tantalum oxide case, there seems to be a dependence in dielectric constant with frequency. At higher frequencies (over about 1 GHz) there is a rapid decrease in the dielectric constant due to relaxation effects. A first order equivalent circuit model has been developed and simulated, showing good agreement with the measurements. Also, the results show a decrease in dielectric constant with decreasing thickness of the films. These preliminary results indicate that the performance of RF-devices and RF-circuits might be seriously degraded in the GHz region. In addition, the DC I-V characteristics were measured in terms of leakage current density and breakdown voltage, and will be presented.
3:40 PM		DI-MoA-6 Interfacial Stability of High-k Dielectrics Deposited by Atomic Layer Chemical Vapor Deposition W. Tsai (IMEC (Intel assignee), Belgium); H. Nohira, R. Carter, M. Caymax, T. Conard, S. De Gendt, M.M. Heyns, J. Petry, O. Richard, W. Vandervorst, E. Young, C. Zhao (IMEC, Belgium); J. Maes, M. Tuominen (ASM Europe, The Netherlands) Control of interfacial oxide growth is critical to achieving sub 1 nm Equivalent Oxide Thickness in high k gate stacks for future generations microelectronic devices. The formation of interfacial oxide is dependent on Si surface preparations, high k dielectrics deposition, post deposition conditioning such as thermal anneal and air exposure. In this work, effect of various interfaces on initial growth of high k layers, interface stability and electrical peformance were investigated. High-k dielectrics layers are grown by Atomic Layer Chemical Vapor Deposition (ALCVD), dielectrics and interfacial layer thickness /composition were characterized by X-ray Fluorescence, X-ray Photoelectron Spectroscopy (XPS) and Transmission Electron Microscopy (TEM). An initial high k dielectrics layer formation with inhibited growth was observed for both ALCVD Al2O3 and ZrO2 films, followed by a linear growth regime with a full coverage layer. For high k dielectrics deposited on Si substrates with hydrogen termination from HF dip, growth of interfacial oxide SiOx was quantified as a function of air exposure. Interfacial oxide forms due to oxygen permeation through the high k layers, either during air exposure; during thermal anneal in an oxygen ambient (>500oC) or during the ALCVD growth itself whereby the growth process itself acts as an oxygen source. The latter is observed in the case of ZrO2 where the interfacial oxide scales with ZrO2 layer thickness. In addition, an intrinsic interfacial oxide growth is observed with XPS from as-deposited high k dielectrics films. For Al2O3, an interfacial oxide of approx. 1.5 Ã… for thickness > 2 nm, reflecting the possible formation of Al-O-Si bond. Minimization of interfacial oxide growth in high k gate stacks was demonstrated with an in-situ poly-silicon cap on Al2O3 to restrict the oxygen diffusion. The stability of such capped high k/ Si interface was also shown to be intact after 1000oC RTP anneal in nitrogen.
4:00 PM		DI-MoA-7 First Step Towards Crystalline Titanate-Si Integration: Formation of Atomic Layer Strontium Silicate on Si(001) S. Gan, Y. Liang, S. Shutthanandan, S. Thevuthasan (Pacific Northwest National Laboratory) Recent work showed that crystalline titanates grown on Si(001) exhibited promising properties as the potential high-K gate oxides for CMOS. One of the critical issues in this approach is the interfacial template layer that needs to possess favorable struc tural and chemical properties for growth of crystalline oxides on Si. We present our recent results on the study of the initial stage of oxide growth on Si(001). Using scanning tunneling microscopy (STM), x-ray photoelectron spectroscopy (XPS), low-energy electron diffraction (LEED), and Rutherford back scattering (RBS), we investigated the structural and chemical behaviors of six strontium based templates grown on Si. It was found that depending on the surface strontium coverage, the strontium-covered Si surfaces exhibit a series of reconstructions. These reconstructions not only had different atomic structures but also different stability against oxidation and the oxide growth. For instance, upon exposure to oxygen, the (3x2) reconstruction was converte d to a disordered (1x1) surface while the Sr/Si-(1x2) reconstruction remained intact. For the growth of oxides, the (1x2) structure was found to provide the most stable interface, as evidenced by a uniform layer in angular dependence XPS results, the lack of interfacial SiO₂ layer, and the ability to form single-crystal SrO films on this structure. By combining results obtained from STM, XPS, RBS, and LEED, we correlated the interface structures with film properties, which allowed us to identify suitable interfacial templates for optimized growth of titanates. Pacific Northwest Laboratory is a multiprogram national laboratory operated for the U.S. Department of energy by Battelle Memorial Institute under Contract DE-AC06-76RLO 1830.a.
4:20 PM		DI-MoA-8 High-k Metal Oxide Dielectrics Deposited by CVD using Oxygen and Ozone M. Yoon, V.K. Medvedev, K.D. Hauch (University of Washington); J.W. Rogers, Jr. (Pacific Northwest National Laboratory); Y. Ono, S.T. Hsu (Sharp Laboratories of America) TiO₂ thin films have generated considerable interest in high-k gate oxide applications. Previously we have described a novel process for creating high purity, carbon-free TiO₂ films on Si utilizing a TiO_x buffer layer.¹ Here, improvements in oxidizing this buffering Ti layer using ozone (O₃) are presented. Auger electron spectroscopy (AES) analysis show similar stoichiometry of Ti and O when using either oxygen or ozone at room temperature. Low energy electron diffraction (LEED) analysis was conducted on Si, Ti/Si, and O₂ oxidized Ti/Si. Preliminary results show: an initial Si substrate with a highly ordered 2x1 structure prior to the deposition of Ti, a crystalline Ti film deposited on the Si, and the amorphorization of the Ti after oxidation with O₂. It is our aim to produce an amorphous TiO₂ film on the TiO_x buffer layer and thus the amorphous structure of this buffer layer is desired. Oxygen deficiency in TiO₂ gate oxide films is a major cause of increased leakage current. O₃ is an attractive alternative to O₂ as an oxidizer since it produces atomic oxygen (O) upon decomposition which can react with single dangling bond sites on the film surface, and thus create a denser, oxygen rich film. The co-deposition of the titanium isopropoxide (TTIP) precursor with O₃ for creating a CVD-TiO₂ film on the buffer layer has been compared to the co-deposition of TTIP with O₂. AES and electron spectroscopy for chemical analysis (ESCA) measurements show few compositional differences between the two TiO₂ films, however, atomic force microscopy reveals distinctly different morphology. The application of TiO₂ and other similarly produced metal oxide films (e.g. HfO₂) as gate oxides in MOS devices is also being explored. ¹A. Tuan, M. Yoon, V. Medvedev, Y. Ono, Y. Ma, and J. W. Rogers, Jr., Thin Solid Films, 377-378 (2000) 766-771.