AVS2001 Session MS-MoP: Aspects of Manufacturing Science and Technology Poster Session
Monday, October 29, 2001 5:30 PM in Room 134/135
Monday Afternoon
Time Period MoP Sessions | Topic MS Sessions | Time Periods | Topics | AVS2001 Schedule
|
MS-MoP-1 Investigations on Post Cu CMP Cleaning of Colloidal Silica Slurry
T.-C. Wang, T.E. Hsieh, S.-Y. Chiu (National Chiao Tung University, Taiwan, R.O.C.); Y.-L. Wang (Taiwan Semiconductor Manufacturing Company); J.J. Chang (National Chiao Tung University, Taiwan, R.O.C.); Y.-N. Shieh (Chang Chun Petrochemical Co., Ltd., Taiwan) Chemical mechanical polishing (CMP) is the only way to achieve the global planarization in copper damascene process. In addition to complex consumables and process controls, one of the key issues in mass manufacturing using CMP technology is post-CMP cleaning. In this study, novel clean solutions for efficient removal of colloidal silica from polished copper line were proposed. There were three kinds of formulated post Cu CMP cleaning solutions carried out including PVA, Dextrose and D-sorbitiol aqueous solution. Cleaning with these chemistries was able to change the character of the colloidal silica abrasive surface and eliminate the strong tendency of the absorption of colloidal silica on copper line. From the SEM images of polished copper surface, abrasive-free Cu surface could be obtained. Besides, the surface-scan for defect analysis performed a different level for Cu CMP post-clean efficiency. In addition, the electrical analyses for polished pattern wafers cleaning were evaluated to verify the performance of these formulated clean solutions. |
|
MS-MoP-2 In-Situ EIS Approaches to the Copper CMP Slurry Characterization
S.-Y. Chiu (National Chiao Tung University, Taiwan, R. O. C.); J.-W. Hsu, Y.L. Tasi (National Tsing Hua University, Taiwan, R. O. C.); Y.-L. Wang (Institute of Materials Science and Engineering, Taiwan, R. O. C.); M.-S. Tsai (National Nano Device Laboratories, Taiwan, R. O. C.); H.C. Shih (National Tsing Hua University, Taiwan, R. O. C.); M.-S. Feng (National Chiao Tung University, Taiwan, R. O. C.) In the chemical-mechanical polishing study, slurry chemistry in chemical-mechanical polishing of Cu thin film has been evaluated in various slurries. Various types of oxidizer and inhibitor were changed in the concentration and slurry pH were investigated. In nitric acid based slurry, with both H+ and NO3- present, it provides a corrosion environment for copper. With citric acid present in slurry system, it plays a role of formation a native passivation film on the surface. The polishing rate of copper increases as the concentration of HNO3 increases or citric acid decreased. In H2O2 based slurry, H2O2 both dissolute of copper and form a cupreous oxide passivation surface. H2O2 is a strong oxidizer, it provides a potential to copper to be oxidized, maybe cupric ion or cuperous oxide simultaneously. For small amount of H2O2 adding in acidic region, it increase the dissolution the copper that increase the polishing rate of copper. With more H2O2 in slurry, the oxide film formation rate increases and the dissolution rate of copper decreases, as a result the CMP removal rate of copper film decreases. With Benzotriazole(BTA) present in HNO3 based slurry, BTA passivated the copper surface from HNO3. And the copper removal is conducted by the abrasive polishing off the BTA from the copper surface then etching the copper surface by HNO3. In this study, we wish to investigate the concentration of oxidizer and inhibitor effect in acidic slurry system on the polishing mechanism of copper CMP. Electrochemical impedance-spectroscopy (EIS) measurements were applied in order to obtain a better fundamental understanding of the electrochemical reaction and the physical model of copper in the CMP process. |
|
MS-MoP-4 Line Type SAC with Oxide Spacer(LSOS) Adopting Flowfill Oxide for 0.10µm Design Rule and Beyond
S.C. Park, S.D. Lee, S.T. Ahn, J.C. Ku, D.S. Kim, J.W. Kim, H.K. Yoon (Hynix Semiconductor, Inc., Korea) In this study, we used Flowfill oxide in the Line-type SAC with Oxide Spacer(LSOS) process, a storage node contact formation technology for DRAM devices. During our LSOS process, a bit-line sidewall was formed after SAC etching, which substantially reduced the aspect ratio of ILD gap-fill process.1 However, for 0.10µm design rule and beyond, even when the LSOS process was applied, small voids were created because conventional High Density Plasma(HDP) oxide was not able to fill the gap between bit-lines. Therefore, we selected Flowfill oxide as a novel InterLayer Dielectric(ILD) material instead of HDP oxide. The key attribute of Flowfill oxide is a unique chemistry of SiH4 and H2O2, which generates a liquid-like intermediate compound that fills very narrow gaps and provides excellent planarity.2 In this experiment, to deposit the Flowfill oxide, TRYKON Planar 200 system was used. A higher Si3N4 selectivity was obtained when Flowfill oxide was used during the SAC etching, compared to HDP oxide. To find the exact cause of such a high selectivity with Flowfill oxide, X-ray Photoelectron Spectroscopy(XPS) was used to analyze partially etched Flowfill oxide and HDP oxide sample. The XPS analysis showed that a thicker fluorocarbon film was formed on Flowfill oxide and the carbon concentration of the fluorocarbon film was higher on Flowfill oxide. The difference of fluorocarbon film can be due to the presence of hydrogen in Flowfill oxide. In addition, we found that even though Flowfill oxide was annealed for the purpose of densification, nano-pores were created at the bottom of the gap between bit-lines. These nano-pores resulted in a partial stoppage of the SAC etching process, so we had to remove the remaining layer during the sidewall etching. Furthermore, we were able to check the practicality of the LSOS process with Flowfill oxide by fabricating a 256Mb density test vehicle having 0.10µm design rule. |
|
MS-MoP-5 Application of Plasma Vdc Bias Diagnostics Cathode For Device Charging Damage Optimization
S. Ma (Applied Materials); K. Horioka (Applied Materials, Japan); R. Lindley, K. Doan, S. Kats, M. Dahimene, Y. Xia, H. Shan (Applied Materials) It is highly desirable to investigate the potential plasma damage issues as early as in the stage of plasma process chamber development without processing the real device wafers. Therefore a diagnostic tool is required to give reliable relationship to real device plasma damage and fast feedback on any process or hardware change. In this paper, a Vdc bias diagnostic cathode is used to measure the plasma induced self bias uniformity across the wafer and the correlation to device charging damage. A Magnetically Enhanced Reactive Ion Etching (MERIE) chamber is used to install this diagnostic cathode. Multiple probe pins are buried within the electrostatic chuck surface with only the top surface tips exposed to plasma. Wafer surface DC bias voltage during plasma process can be directly measured from these probes simultaneously with built-in circuitry. Real-time analysis of Vdc bias is thus feasible by multi-channel recording of bias evolution. The maximum bias difference (δVdc = Vdc(max) - Vdc(min)) between the maximum and the minimum value of simultaneously measured Vdc across the cathode surface can be used to correlate to the potential driving voltage on the wafer to generate device damaging current during plasma process. Compared to real antenna MOS capacitor device damage data under similar process conditions, when δVdcis less than a threshold around 12V then plasma induced charging damage is not a concern. This method also shows successful examples of different process recipes and hardware optimization to meet industrial device plasma damage spec. |