AVS2001 Session MM-ThP: Poster Session
Thursday, November 1, 2001 5:30 PM in Room 134/135
Thursday Afternoon
Time Period ThP Sessions | Topic MM Sessions | Time Periods | Topics | AVS2001 Schedule
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MM-ThP-1 Determination of the Young's Modulus and Residual Stress in 3C-SiC Films Using the Load-Deflection Technique
J. Mitchell, C.A. Zorman, M. Mehregany (Case Western Reserve University) Silicon Carbide is an attractive mechanical material for MEMS due to its high Young's modulus coupled with its high temperature stability and chemical inertness. SiC is also receiving attention as a material for NEMS for these same reasons. The cubic polytype (3C-SiC) can be epitaxially grown on (100)Si substrates, thus providing an excellent opportunity for measuring the mechanical properties of SiC, since test structures can be fabricated using conventional Si bulk micromachining techniques. Using an interferometric load-deflection technique applied to bulk micromachined diaphragms, we have measured the spatial distribution of the Young's modulus and residual stress of 3C-SiC films grown on large-area (100 mm-dia.)(100) Si wafers. In addition to the spatial distribution, the run-to-run variation and the variation as a function of film thickness were also characterized. In general, we found that the Young's modulus, which averaged about 360 GPa, is insensitive to location on the wafer as well as film thickness. This is in stark contrast to the residual stress, which varied by as much as 200 MPa across a 100 mm-diameter wafer, and is, in general, higher for thinner films. This paper will detail the film growth process, and test sample preparation procedure, the testing technique, and the test results for 3C-SiC film thicknesses ranging from 0.125 to 2 microns. Issues pertaining to making measurements of high modulus films such as SiC using the load-deflection technique will also be discussed. |
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MM-ThP-2 A Trench Etching Technique Using MERIE to Fabricate MEMS Accelerometers
K.-W. Kok (National University of Singapore, TEMIC Automotive (Singapore) Pte Limited); W.J. Yoo (National University of Singapore) Plasma etching is an important process to form deep high aspect ratio beams in fabrication of MEMS devices. Properties pertaining to the anisotropic trench etching process have been studied using SiF4/HBr/NF3/HeO2 gas mixtures by a magnetically enhanced reactive ion etcher (MERIE). We investigated the taper angle and etching rate in the trenches, the dependency of the etching rates on pattern-size and open area ratio, and roughness on the sidewall. The etching masks of SiO2 and Si3N4 were used. In these conditions, etching selectivities of the silicon substrate with respect to the etching mask were in the range of 60 to 120 for the SiO2 mask and these were about three times higher than for the Si3N4 mask. The high etching selectivities from the SiO2 mask resulted in the steep trench profile and this made possible to form the deep trench structures of the aspect ratio of 25. Furthermore, the open area ratio on the wafer was varied in the range of 10% to 50% to determine loading effects which are problematic in inductively coupled plasma (ICP) etching. Etching rates and their uniformity across the wafer in the ICP were known to be strongly affected by the open area ratio. We found that, in the MERIE, the etching rates remained constant and their uniformity was less than 2% regardless of the open area ratio for the all pattern sizes investigated. The surface roughness on the sidewall was maintained within 5nm after deep trench etching up to 20mm, and the electrical test proved that this was acceptable to control capacitance of the MEMS accelerometers accurately. |
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MM-ThP-3 Micro-fabrication of a Novel n-channel Field Effect Transistor Cantilever to Sense Charge Traps
M.S. Suh, G.H. Yon, Y. Kuk (Seoul National University, Korea) We have micro-fabricated a novel n-channel field effect transistor (FET) cantilever that is proposed to sense surface potential profile in nanometer scale. Conventional techniques used in surface and bulk micro-electromechanical system (MEMS) and combined complementary metal oxide semiconductor (CMOS) process have been employed to make a novel n-channel FET cantilever made of silicon on insulator (SOI) wafers. The cantilevers with various beam lengths, width, and thickness have been fabricated and their resonance frequencies were measured. Thermal annealing after high-dose ion implantation controlled the channel length between the source and the drain. This cantilever resembles nchannel metal oxide semiconductor FET (n-MOSFET) without a gate electrode. If a biased or charged sample is positioned closed to the cantilever, it works as the gate electrode. The device characteristics of the novel FET cantilevers were similar to the conventional n-MOSFET. |