Papers

AVS2001 Session MS-TuM: Process Integration and Factory Productivity

Tuesday, October 30, 2001 8:20 AM in Room 131

Tuesday Morning

Start	Invited?	Item
8:20 AM		MS-TuM-1 Reduction in Loadlock Vent Time and Particles through Use of Fast Vent Diffuser C. Adcock (Mykrolis Corporation (Formerly the Microelectronics Division of Millipore Corporation)); H. Dang (Texas Instruments Inc.); J. Gratz, M. Randolph, J. Snow, C. Tsourides (Mykrolis Corporation); R. Wheeler (Millipore Corporation) Improvements to semiconductor manufacturing equipment effectiveness can be directly impacted by enhancements in tool throughput and/or product yield. One area for these improvements is system loadlocks. Reducing loadlock vent-up time from vacuum to atmospheric pressure increases tool throughput. Additionally, reducing particle adders in the loadlock increases product yield. Traditionally, a soft vent procedure has been used in an attempt to balance loadlock vent-up time with reduced particle generation. While some particle control is achieved, vent-up times are often in excess of ten minutes - not an optimal solution. Gas diffuser technology has been developed and integrated with filtration technology to enable faster vent-up of loadlocks while simultaneously decreasing particle adders on the wafer. This is accomplished using a "specially formulated" sintered porous metal membrane, which provides laminar flow across the entire diffuser surface. Vent gas volume is maximized while gas velocity at the loadlock entrance is minimized. Results from two independent evaluations with diffusers will be presented. First, tests conducted at an equipment manufacturer will demonstrate an 80% reduction in vent time with no adverse effect on particle performance. Second, on-tool performance at a semiconductor manufacturing facility will highlight the reduction in wafer particle adders.
8:40 AM		MS-TuM-2 Cleaning Procedures in Wafer Processing: Analytical Challenges for Root Cause Determination of Particle Problems C.C. Wang, Y.S. Uritsky, C.R. Brundle (Applied Materials, Inc.) Common dry clean procedures used in the wafer processing industry are: substrate pre-clean of individual wafer prior to deposition (gentle Ar⁺ sputter), and hardware clean after many processed wafers to remove the sputtered material build-up (harsh NF₃ usually). Particle failures can result from both procedures, however, and are a severe industry problem. In the Ar⁺ pre-clean a gradual build-up of by-products of cleaning occurs on chamber surfaces. These can chemically react with the hardware material, releasing composite particles through stress (proven by detailed particle morphology observation). In the NF₃ case, the fluorine radicals, intended for removing deposits by forming volatile products, often attack hardware itself producing particles. In both cases particle analysis is critically needed to determine exactly what piece of hardware is being attacked and by what mechanism for the purpose of hardware and process improvements. The sophistication of the analytical work required for finding root cause is high. In this paper we describe how careful SEM/EDX work, supported by FIB and Raman/Photoluminescence, identified root cause in both NF₃ and Ar⁺ clean particle failures. In the NF₃ case the critical issue was to establish, without any doubt, that generated particles scavenged by an oxide monitor wafer, contained no oxygen and only Al and F. In the Ar⁺ pre-clean case it was demonstrated that particles consisted of thin, plate-like bi-layers of sputtered substrate material (SiON in this case) and amorphous Al₂O₃ from the surface of the plasma degraded ceramic dome. In both cases modeling the EDX spectra using STRATAGEM¹ software for multi-layer thin film structures (and here applied to particles) was important in reaching definitive conclusions, which were then used in the successful defect reduction actions. ¹ STRATAGEM is a registered trademark of SAMx.
9:00 AM		MS-TuM-3 High Productivity Plasma Etch Reactors: Hardware and Chemistry Concepts D. Podlesnik (Applied Materials)
9:40 AM		MS-TuM-5 Data Driven Manufacturing C.J. Spanos (University of California, Berkeley) Manufacturing has evolved through several stages: From handmade parts, to interchangeable components, from scientific management and statistical process control to numerical control, and finally to intelligent machine tools and flexible production facilities. While it took over 200 years for traditional manufacturing to mature, semiconductor manufacturing advanced through all these stages in four short decades. More so than in other types of manufacturing, today's semiconductor manufacturing is "data driven" in many levels of abstraction. Much like traditional manufacturing, there is tremendous data infrastructure at the factory level, monitoring parts movement, recipes, consumables, etc. Unlike traditional manufacturing, however, there is also data driving the production at the process or tool level. Examples here include the sophisticated control and diagnosis databases that often describe individual process steps of critical nature, such as plasma etching, photolithography and Chemical-Mechanical Planarization. An additional example of unusual datasets in semiconductor manufacturing has to do with the large amount of wafer or work-piece data, collected to monitor tooling, to predict yield, to drive control applications, and to also drive the evolution of semiconductor manufacturing technology. This talk will examine this hierarchy of data in semiconductor manufacturing, and it will specifically focus on the interactions between the various levels. Examples will be given regarding critical deep sub-micron patterning steps of the semiconductor manufacturing sequence.
10:40 AM		MS-TuM-8 Gate Module Integration with High k Dielectrics S.W. Butler (Texas Instruments) Due to silicon dioxide being unable to meet future gate dielectric thickness and leakage requirements, silicon dioxide as a gate dielectric is being replaced with a higher k material, such as a metal silicate. Switching from silicon dioxide to a higher k dielectric involves more than just changing the dielectric. Although the goal is to minimize changes to a traditional CMOS flow, this paper will discuss the reality of the types of changes that must be made for the transistor to achieve improved performance and meet the SIA Roadmap requirements. Temperature changes are the most common type of change considered. However, there are more subtle process and flow changes which can be quite insidious and their impact must be understood. Contamination concerns may also drive process changes, but are more likely to cause procedural or manufacturing system changes. Such changes may be considered more expensive by a production fab than a process or equipment change.