AVS 72 Session AM2+EM+TF-WeA: Devices I

Gallium oxide (Ga₂O₃) has recently attracted significant attention as an ultra-wide-bandgap semiconductor for next-generation high-power electronic devices. In high-power applications, device operation generally relies on high voltage and low current to reduce conduction losses. However, conventional device design faces a trade-off between reducing on-resistance and maintaining high breakdown voltage, as thinner drift layers lower resistance but also degrade voltage endurance. To address this limitation, materials with high critical electric fields are essential. Ga₂O₃ offers a significantly higher critical electric field than conventional semiconductors such as Si and SiC, enabling high breakdown voltage operation even at reduced thickness, thereby improving power efficiency. Nevertheless, its low thermal conductivity remains a critical challenge due to heat accumulation and potential thermal breakdown. In this work, high-quality Ga₂O₃ thin films with a rocking curve full width at half maximum (FWHM) of approximately 0.3° were achieved, indicating excellent crystalline quality. The Ga₂O₃ films were epitaxially grown on two-dimensional artificial mica substrates and subsequently transferred onto high-thermal-conductivity copper foils to enhance heat dissipation. In addition, a pn heterojunction composed of 600 nm-thick Ga₂O₃ and NiO was fabricated, exhibiting a breakdown voltage exceeding 500 V. The proposed structure simultaneously preserves high-voltage capability and improves thermal management, demonstrating a promising approach for high-power Ga₂O₃-based electronic devices.

4H-SiC Schottky barrier diode (SBD) devices were fabricated on n-type 4H-SiC substrates using an ultrathin nickel film of 2 nm as the Schottky contact layer, deposited via electron-beam evaporation. First, the ohmic contact was formed using 100 nm of nickel, and the samples were annealed at 950 °C for 5 minutes. Subsequently, 2 nm of Ni was deposited, and the devices were subjected to various annealing temperatures. To create the metallic contact, 300 nm of Al was deposited by thermal evaporation and patterned into pads of 2 mm diameter without any shielding structure. The influence of annealing temperature on electrical performance and interface quality was evaluated. Electrical characteristics were measured using a parameter analyzer, and surface morphology was analyzed by atomic force microscopy (AFM). For comparison, reference SBDs with a conventional 100 nm Ni film were fabricated and characterized under identical conditions.

A set of samples was annealed at temperatures ranging from 500 to 700 °C in 50 °C steps for each sample. After the annealing treatment, the final thickness was approximately 8 nm, as measured by AFM. Electrical measurements showed that diodes were obtained at all annealing temperatures, but the best electrical performance was achieved at 650 °C, with devices annealed at 500 °C and 700 °C showing inferior rectifying behavior. For comparison, a reference Schottky diode with a 100 nm thick Ni film was fabricated. The results revealed that the 2 nm diodes exhibited a Schottky barrier height (SBH) of 1.2 eV compared to 1.6 eV for the 100 nm diodes. However, the 2 nm diodes showed a rectification ratio two orders of magnitude larger and a leakage current of 22 pA compared to 3.2 nA at -200 V. Leakage current was also measured as a function of temperature from 25 to 175 °C. From 25 °C to 50 °C, the leakage current was approximately five times lower for the 2 nm devices compared to the 100 nm devices. Finally, the density of interface states was extracted from the 2 nm device, yielding a value of 10¹²cm^-2eV^-1, while the 100 nm device showed values around 10¹³ cm^-2eV^-1.

For future analysis, devices with lateral shielding will be fabricated to compare the breakdown voltage. Additionally, HRTEM and XPS characterization will be performed to verify the silicide composition stoichiometry and the presence of undesirable carbon clusters.

Field-emission-based nanoscale vacuum-channel transistors (NVCTs) can combine the robustness of vacuum devices with state-of-the-art lithography techniques enabling low operating power, on-chip integrability, energy efficiency, and high-performance stability in extreme environments such as high temperatures and high radiation. By scaling device channels to be below the electron’s mean-free path in air, the NVCTs can be operate in air while maintaining the ballistic electron transport characteristic of vacuum. Here, we report experimental and modeling results of top-down fabricated, single emitter gallium nitride (GaN) lateral NVCTs. We used electron beam lithography along with dry and wet etching to fabricate GaN NVCTs with device channel lengths less than 60 nm. The devices exhibited stable high field-emission current up to 100 nA, with tuning on/off ratio greater than 10³. Minimal leakage current from the gates was observed to be less than 0.1 nA. Finite-element (COMSOL) modeling showed strong electric field penetration of GaN emitter led to emission current modulation by the gate voltage. This study elucidates the operation of field emission based lateral gated devices and provides important understanding in the design and operation of these new class of devices. Sandia National Laboratories is managed and operated by NTESS under DOE NNSA contract DE-NA0003525. This work was performed, in part, at the Center for Integrated Nanotechnologies, a U.S. Department of Energy, Office of Basic Energy Sciences user facility. This paper describes objective technical results and analysis. Any subjective views or opinions that might be expressed in the paper do not necessarily represent the views of the U.S. Department of Energy or the United States Government.