Inspired by the efficiency of the brain, CMOS-based neural architectures and memristors are being developed for pattern recognition and machine learning. However, the volatility, design complexity and high supply voltages for CMOS architectures, and the stochastic and energy-costly switching of memristors complicate the path to achieve the interconnectivity, information density, and energy efficiency of the brain using either approach. In my talk, I will review the latest advances in neuromorphic computing architectures based on deep neural networks implemented using CMOS and memristors and describe the challenges in achieving both high accuracy and energy efficiency using these devices. I will then discuss an alternative approach based on the non-volatile redox memory (NVRM): a device with a resistance switching mechanism fundamentally different from existing memristors, involving the reversible, electrochemical reduction/oxidation of a material to tune its electronic conductivity. The first type of NVRM that I will describe is based upon the intercalation of Li-ion dopants into a channel of Li_1−xCoO₂. This Li-ion synaptic transistor for analog computing (LISTA) switches at low voltage (mVs) and energy, displays hundreds of distinct, non-volatile conductance states within a 1V range, and achieves high classification accuracy when implemented in neural network simulations¹. The second type of NVRM I will describe operates on a similar principle but is based on the polymer system PEDOT:PSS, and which we call the electrochemical neuromorphic organic device (ENODe) ². Plastic ENODes are fabricated on flexible substrates enabling the integration of neuromorphic functionality in stretchable electronic systems. Mechanical flexibility makes ENODes compatible with three-dimensional architectures, opening a path towards extreme interconnectivity comparable to the human brain.

1) E. J. Fuller et al., Advanced Materials 29, 1604310 2017.

(2) Y. B. van de Burgt et al., Nature Materials 16, 414 2017.

(3) S. Agarwal et al., IEEE 2017 Symposium on VLSI Technology Digest of Technical Papers, DOI: 10.23919/VLSIT.2017.7998164.

1)Memristor Kinetics and Diffusion Characteristics for Mixed Anionic-Electronic SrTiO3-δ: The Memristor-based Cottrell Analysis Connecting Material to Device Performance F Messerschmitt, M Kubicek, S Schweiger, JLM Rupp Advanced Functional Materials, 24, 47, 7448 (2014) >

2)Uncovering Two Competing Switching Mechanisms for Epitaxial and Ultra-Thin Strontium Titanate-based Resistive Switching Bits M Kubicek, R Schmitt, F Messerschmitt, JLM Rupp ACS Nano 9, 11, 10737 (2015) >

3)Designing Strained Ionic Heterostructures for Resistive Swicthing Devices S Schweiger, R Pfenninger, W Bowman, U Aschauer, JLM Rupp Advanced Materials, (2016) >

4) The Effect of Mechanical Twisting on Oxygen Ionic Transport in Solid State Energy Conversion Membranes Y Shi, AH Bork, S Schweiger, JLM Rupp Nature Materials, 14, 721 (2015) >

5) A Micro-Dot Multilayer Oxide Device: Let’s Tune the Strain-Ionic Transport Interaction S. Schweiger, M. Kubicek, F. Messerschmitt, C. Murer, J.L.M. Rupp ACS Nano, 8, 5, 5032 (2014) >

6) How does Moisture affect the Physical propert of Memristance for Anionic-Electronic Resistive Switching Memories? F Messerschmitt, M Kubicek, JLM Rupp Advanced Functional Materials, 25, 32, 5117 (2015) >

As CMOS scaling approaches its limits, it becomes more difficult to keep improving the speed-energy efficiency of traditional digital processors. To address this issue, computing systems augmented with emerging devices particularly memristors, offer an attractive solution. Memristors use conductance to represent analog or digital information. The dynamic nature of memristor with both long-term and short-term memories, together with its small effective size contributes to the energy efficiency in weight updating (training). The in-memory computing scheme in a crossbar breaks the ‘von Neumann bottleneck’ as the weights are stored locally in each device during computing. The read out (inference) is finished in one clock cycle regardless of the array size, offering massive parallelism and hence high throughput. The capability of using physical laws for computing in a crossbar enables direct interfacing with analog signals from sensors without energy- hungry analog/digital conversions.

We developed a Ta/hafnium oxide memristor with stable multilevel resistance, linear current voltage characteristics in chosen conductance ranges, in addition to high endurance and long retention. We further integrated the memristors with foundry-made transistors into large arrays. We demonstrated that the reconfigurable memristor networks are capable of analog vector matrix multiplication, and successfully implemented a number of important applications including signal processing, image compression and convolutional filtering. We also built a multilayer memristor neural network, with which we demonstrated in-situ and self-adaptive learning capability with the MNIST handwritten digit dataset. The successful demonstration of analog computing and in-situ online training suggests that the memristor neural network is a promising hardware technology for future computing.

Inspired by the superior capability of the brain, neuronal spiking, and synaptic behavior have been mimicked by the CMOS-based neuronal cell in hardware, which contains 6-12 transistors depending on specific functionality and the robustness of the design. However, the higher energy consumption and physical area have led researchers to look for architectures based on single device and novel materials.

In our work, utilizing thin-film vapor-liquid-solid growth method, we fabricated scalable Indium phosphide (InP) channel transistors directly on Si/SiO₂ wafer, which can emulate significant synaptic characteristics such as elasticity, short- and long-term plasticity, metaplasticity, spike number dependent plasticity and spike timing dependent plasticity, by modeling gate electrode as the pre-synaptic axon terminal, the drain electrode as the post-synaptic dendrite, and the gate oxide-semiconductor channel as the synapse junction, in which we also interpreted the FET channel conductance as the synaptic weight.

We also demonstrated that by controlling the charging and discharging of interfacial traps at the gate oxide-semiconductor stack, we can essentially engineer hysteresis of the synaptic device to customize the synapse behavior and modify the synapse weight non-linearly. It underpins optimal selectivity of signal transduction and satisfies the key neuromorphic architecture characteristic—training and learn. Tuning hysteresis in a family of transfer characteristics in spike timing dependent plasticity (STDP) emulation, we attain maximum potentiation (depression) for the minimum positive (negative) interval time, which gradually decays down to elasticity, as we expected, indicating the scalable InP channel transistors on silicon as promising devices and platform for neuromorphic computation.

Voltage or current controlled oscillators are well-established candidates for solid-state implementations of neurons. Metal to insulator transition (MIT) based phase change electrical oscillators are one of the many candidates for solid-state neurons, but current implementations are far from the ideal performance limits of energy and time necessary to induce the transition. We propose the use of nanoscale, epitaxial heterostructures of phase change oxides such as VO₂, NbO₂ and oxides with metallic conductivity as a fundamental unit of a low power electrical oscillator, capable of operating as neurons for neuromorphic computing architectures. Our simulations such that such oscillators can operate in the microwave regime and overcome many of the power consumption issues plagued by phase change electrical oscillators.

Artificial neural networks are performing tasks, such as image recognition and classification, that were thought only accessible to the brain. However, these algorithms run on traditional computers and consume orders of magnitude more energy more than the brain does at the same task. One promising path to reduce the energy consumption is to build dedicated hardware to perform cognitive tasks. Nanodevices are particularly interesting because they allow for complex functionality with low energy consumption and small size. I discuss two nanodevices. First, I focus on stochastic magnetic tunnel junctions, which can emulate the spike trains emitted by neurons with a switching rate that can be controlled by an input. Networks of these tunnel junctions can be combined with CMOS circuitry to implement population coding to build low power computing systems capable of processing sensory input and controlling output behavior. Second, I turn to different nanodevices, memristors, to implement a different type of computation occurring in nature: swarm intelligence. A broad class of algorithms inspired by the behavior of swarms have been proven successful at solving optimization problems (for example an ant colony can solve a maze). Networks of memristors combined with CMOS circuitry can perform swarm intelligence and find the shortest paths in mazes. These results are striking illustrations of how matching the functionalities of nanodevices with relevant properties of natural systems open the way to low power hardware implementations of difficult computing problems.