The integration of high carrier mobility materials into future CMOS generations is presently being studied in order to increase drive current capability and to decrease power consumption in future generation CMOS devices. If III-V materials are the candidates of choice for n-type channel devices, antimonide-based III-V semiconductors present the unique property of owning both high electrons (InSb) and holes (GaSb) mobilities, which triggered much of the interest in these III-Sb compounds for advanced CMOS. Moreover recent simulations have demonstrated that higher hole mobility could be found in strained III-antimonides compounds, suggesting the possibility of an all III-antimonide solution for full III-V based CMOS. In this work we studied the heteroepitaxy of 6.1 family semiconductors (GaSb, AlSb & InAs) on various III-V and Si substrates as well as the passivation of such semiconductors.

The relatively large lattice parameter of “6.1” semiconductors makes the growth and the integration on standard surfaces difficult. But is it possible to grow such semiconductors fully relaxed with low defect density due to the formation of a highly periodic array of 90º misfit dislocations at the III-Sb/substrate interface. In this contrbution both MBE and MOVPE growth techniques have been studied in order to propose novel integration scheme on Si substrate.

In a second part, we will focus on the passivation of these III-V semiconductors. Because III-V surfaces are very sensitive to oxygen compounds, this will generate the formation of native oxide. This undesirable interlayer will contribute aggressively to the high density of surface states within the energy band gap, resulting in Fermi level pinning which disturbs the basic III-V MOSFET-operation. In this context both ex-situ and in-situ Al₂O₃ high-κ gate dielectric deposition by standard ALD or MBD processes is reported. The interface is abrupt without any substantial interfacial layer, and is characterized by high conduction and valence band offsets. Finally, MOS capacitors showed well-behaved C-V with relatively low D_it along the band gap. Such a D_it profile is promising for the future devices and suggests possibility to attain a low subthreshold swing.

Due to its high hole mobility and relative compatibility with Si CMOS processing, Ge has long been considered as a replacement channel material for PMOS devices. Selective area growth of Ge channels on bulk Si substrates would be ideal for minimizing fabrication costs and allowing the co-implementation of other materials (III-Vs for NMOS). However, due to the 4.2% lattice mismatch between Ge and Si, unacceptably high dislocation densities (~10⁹ cm^-2) are created during this heteroepitaxy.

In this work, we investigate the fabrication of MOS gate stacks on MBE-grown Ge on Si using Aspect Ratio Trapping (ART)^1,2 to reduce Ge defect density. ART is a growth technique that allows for the reduction of defects for lattice mismatched materials by trapping the threading dislocations into the sidewalls of patterned nanoscale trenches in which the epitaxial growth takes place. This technique has the added benefit of producing the necessary geometric structure required for highly scaled tri-gate devices while reducing defect density simultaneously. Surface roughness and defect density dependence on growth temperature and growth rate will be discussed as will be the effect of varying the trench geometry. RHEED, XRD, XPS, TEM, EPD, AFM, SEM, and IPE data are correlated with growth conditions to produce high quality heteroepitaxial growth. Data will be presented demonstrating the use of low-temperature buffer layers in conjunction with low-growth rate bulk Ge results in a reduction in threading dislocations of 2-3 orders of magnitude.

MOS devices were fabricated on the MBE-grown Ge on Si samples. A high-quality interface was obtained using a DI-H₂O surface functionalization by pre-pulsing the H₂O 50 times in the atomic layer deposition (ALD) chamber at 250 °C.³ A thin interfacial Al₂O₃ film was deposited by ALD at 250 °C followed by forming gas anneal (FGA) performed for 30 minutes at 350 °C. This FGA step converts the surface functionalized oxide to a thin layer of GeO₂ resulting in improved electrical performance. 2.5 nm of HfO₂ was then deposited by ALD. 10 nm of RF sputtered TiN was deposited as the gate metal followed by low-temperature anneals in various ambients to tune the effective work function of the HfO₂/TiN gate stack.⁴ A final FGA for 30 minutes at 350 °C completed device processing. These devices show excellent PMOS characteristics and will be discussed.

This work is supported by the SRC Global Research Corporation.

1 J.-S. Park, et al., Appl. Phys. Lett. 90, 052113 (2007).

2 J. Bai, et al., Appl. Phys. Lett. 90, 101902 (2007).

3 S. Swaminathan, et al., J. Appl. Phys. 110, 094105 (2011).

Current status and challenges of aggressive equivalent-oxide-thickness (EOT ) scaling of high-k gate dielectrics via higher-k (>20) materials and interfacial layer (IL) scavenging techniques are reviewed [1]. La-based higher-k materials [2, 3] and La-silicate IL with HfO₂ [4] showed aggressive EOT values (0.5–0.8 nm), but with large effective workfunction (EWF) shifts toward the Si conduction band edge, limiting their application to nFET. Further exploration for pFET-compatible higher-k materials is needed. Meanwhile, IL scavenging is a promising approach to extend Hf-based high-k dielectrics to future nodes [4, 5]. Remote-scavenging techniques enable EOT scaling below 0.5 nm. We will review IL scavenging techniques from the viewpoints of (1) IL growth condition; (2) Choice of scavenging element; (3) Location of scavenging element; (4) Choice of high-κ material and (5) Maximum process temperature. Careful choice of materials and processes based on these considerations is indispensable. Mobility-EOT trends in the literature suggest that short-channel performance improvement is attainable with aggressive EOT scaling via IL scavenging or La-silicate formation. However, extreme IL scaling is accompanied with loss of EWF control [6] and with severe penalty in reliability [7]. Therefore, highly precise IL thickness control in an ultra-thin IL regime (<0.5 nm) will be the key technology to satisfy both performance and reliability requirements for future CMOS devices.

This work was performed by the Research alliance Teams at various IBM Research and Development Facilities.