Nanoscale integration of dissimilar materials with distinct compositions, structures and properties has the potential to create a new generation of integrated systems with unique functions and/or unprecedented performance to break the boundaries of traditional technologies. In this talk, I will focus my discussion on the heterointegration of graphene with a variety of nano and molecular scale structures of designed architectures to open up exciting opportunities for nanoscale device egineering. In particular, I will discuss our recent effort in integrating graphene with a self-aligned nanowire gate to create the highest speed graphene transistors, integrating graphene with plasmonic nanostructures to create multi-color high speed photodetectors, integrating graphene with nanoscale templates for the creation of graphene nanostructures, and integrating graphene with various π-conjugating molecular systems for band gap engineering and molecular sensing.

Graphene is a topic of very active research from basic science to potential applications. Various RF circuit applications are under evaluation, which include low-noise amplifiers, frequency multipliers, mixers and high-speed radiometers. Potential integration of graphene on Silicon substrates with CMOS compatibility would also benefit future RF systems. The future success of the RF circuit applications depends on vertical and lateral scaling of graphene MOSFETs to minimize parasitics and improve gate modulation efficiency in the channel. In this presentation, we highlight recent progress in graphene materials and devices. For example. with hydrogen intercalation, a graphene wafer showed an electron mobility of 2500 cm²/Vs at 6.8 x 10¹² /cm² carrier density, and sheet resistance of 230 ohm/square. The Ti-based ohmic contact resistance is below 100 ohm*µm and hysteresis in HfO₂/Graphene MOSFET transfer curves are no longer concerns in RF applications. We will show graphene MOSFETs in mixer and detector applications with performances comparable to and better than the current state-of-the-art technologies. Also, we will present recent process in graphene heterostructure based diodes with on/off ratio greater than 10⁶. In summary, while graphene is relatively new material, it shows a strong potential to become disruptive in RF applications.

This work was partially supported by DARPA, monitored by Dr. J. Albrecht, under SPAWAR contract number N66001-08-C-2048.

The views, opinions, and/or findings contained in this article/presentation are those of the author/presenter and should not be interpreted as representing the official views or policies, either expressed or implied, of the Defense Advanced Research Projects Agency or the Department of Defense.

[1] J. S. Moon and D. K. Gaskill, IEEE Trans. Microwave Theory and Techniques, p. 2702, 2011

Scalable high-κ dielectric integration is needed to realize graphene-based THz transistors. Yet, the inert nature of graphene inhibits direct application of high-quality uniform atomic layer deposition (ALD) dielectrics. While several methods have rendered the surface more susceptible to ALD[1], they often degrade mobility and/or shift the Dirac voltage due to charges within the gate stack. Recently, we developed a dry chemical functionalization approach using XeF₂ that results in conformal, thin high-κ ALD oxide films with a 10-25% improvement in graphene mobility[2], high dielectric constants (HfO₂=18.5, Al₂O₃=8.9), and small Dirac voltage shifts (HfO₂=2V, Al₂O₃=0.1V), indicating the effectiveness of F functionalization. We will present in-depth details of our fluorination process, discuss its advantages and limitations with respect to other methods used to enhance ALD reactivity with graphene, and provide future directions for this field of study.

Fluorination of EG surfaces was performed in a Xactix X3 XeF₂ etcher operating in pulse mode. Results show that 15 nm pinhole-free Al₂O₃ and HfO₂ films are obtained with an optimized XeF₂ surface treatment prior to ALD consisting of six, 20s pulses (XeF₂=1 torr, N₂=35 torr). This optimal treatment resulted in ~6% fluorine surface coverage, as semi-ionic C-F bonds (F1s ~687eV) only, which provided additional ALD reaction sites needed to obtain uniform oxide films. This unique semi-ionic nature of the C-F bond allows the graphene lattice to maintain planarity and minimize degradation to transport properties.

Theoretical studies suggest that the semi-ionic nature of the C-F bond is related to the graphene electron sheet carrier density (n_e), requiring at least 10¹³ cm^-2 to form[3]. To test this, EG samples with similar thickness but varying n_e (2x10¹²-1.3x10¹³ cm^-2) were fluorinated simultaneously using the optimal conditions above. Samples with n_e >1x10¹³ cm^-2 had only semi-ionic C-F bonding, but those with n_e <1x10¹³ cm^-2 had both covalent and semi-ionic bonding – verifying the theoretical calculations. The amount of covalent bonding increased as n_e decreased, and an increased pinhole density was seen in subsequent Al₂O₃ films. This implies that the underlying EG properties can impact the effectiveness of this fluorination method. Yet, by adjusting the pulse conditions one can tailor this method to still obtain uniform ALD oxides on low carrier density and even p-type EG. To this end, results of our XeF₂ approach on p-type H₂ intercalated EG samples will be shown.

1. Garces,et.al. JVST B 30(3) 03D104 (2012)

2. Wheeler,et.al. Carbon50 2307 (2012)

3. Sofo,et.al. Phys Rev B 83(8) 081411(R) (2011)

The growth of high quality insulating films on graphene is a crucial materials science task for the development of graphene-based spintronics because graphene is a potentially revolutionary material for electronic and spintronic applications. For efficient spin-injection, graphene is expected to suffer from the well known “conductivity mismatch” problem at metal-semiconductor spin electrode interfaces. The standard approach to mitigating this problem has been to grow thin, insulating tunnel barriers between the graphene and the magnetic metallic electrode to provide a spin-dependent resistance via the tunneling magnetoresistance effect. It has been demonstrated by several experiments that direct spin injection from a magnetic electrode to graphene is possible but using aluminum oxide or MgO tunnel barriers to assist injection in graphene spin-valve devices is more efficient if suitable oxide-graphene interfaces can be formed. To address this problem we have used pulsed laser deposition (PLD) to grow thin (1-1000 nm) magnesium oxide films directly on epitaxial graphene on SiC(0001). We observe very smooth film morphologies (typical rms roughness of ~0.4 nm) that are nearly independent of film thickness and conform to the substrate surface which had ~0.2 nm rms roughness. Surface roughness is less than 0.5 nm for thicknesses up to 1000 nm and is independent of deposition laser pulse energy within the range 300-700 mJ/pulse at rates of 1-50 Hz. X-ray diffraction shows predominant (111) and (100) orientations, indicating the possibility of doping the graphene by the polar (111) interface. Raman spectroscopy indicates that the graphene is not measurably damaged by magnesium oxide growth. This work shows that PLD is a good technique to produce graphene-oxide interfaces without pre-deposition of an adhesion layer. The films are free of defects or pinholes (that can be observed by atomic force microscopy) and can be grown at arbitrary thicknesses without increasing the roughness or damaging the graphene. The details and kinetics of the deposition process will be described with comparisons being made to other dielectric-on-graphene deposition approaches.

In this study we investigate the use of a self-assembled monolayer (SAM) to create a p-n junction in graphene films. Previous techniques rely on charge transfer from adsorbants or electrostatic gate/potentials. Here we demonstrate that, by successfully modifying the SiO₂ surface with an aminopropyltriethoxysilane (APTES) layer, and using intrinsically p-doped transferred CVD graphene films, a well-defined junction can be achieved. Field-effect transistors and p-n junction regions are fabricated prior to graphene film transfer, in order to preserve the pristine properties of the graphene. The I-V characteristic curve indicates the presence of two thermally-controllable neutrality points. This method allows a facile, controllable and low temperature fabrication of graphene p-n junctions.

It is now widely accepted that surface contaminants have large effects on the performance of graphene-based field effect transistors. Various techniques are now available to clean processing residues from graphene, yet some of these techniques are chemically aggressive leaving concerns that they may damage graphene and affect the device performance. In addition, there are no concensus on the best method to produce the cleanest and, therefore, the best graphene devices.

Here, we have performed a study on the impact of various chemical treatments on the performance of field effect transistors fabricated from graphene grown using chemical vapor deposition. By measuring the impact of hydrogen-annealing, oxygen-annealing, and various solvent-based cleaning on 50 graphene field effect transistors, we generate a statistically-significant conclusion on the best cleaning technique for producing the highest performance. We will present our results along with our scanning tunneling microscopy images and Raman spectra to shed a light on the mechanism involved in each cleaning technique.