Portability and performance are becoming the main two keywords in any consumer or professional applications. Portable computers, mobile phones, handheld measurement instruments, and many other examples are all applications that need long battery lifetime while compromising the least at the performance level. Long battery lifetime is simply translated into less power consumption and hence operating at lower voltage schemes. This new approach requires solutions at all levels; including material, fabrication, device structure, circuit design, and system architecture. Wideband characterization is the bridge that links these levels together (especially material, fabrication and device structure levels) and provides the means to optimize this cycle of innovation for an optimized final product in the Low Voltage Low Power (LVLP) regime.

Wideband characterization is the process of measurement and extraction of many parameters of the Device-Under-Test (DUT) in order to fully understand its characteristics and be able to provide solutions for inconvenient performance aspects. Wideband characterization usually covers a wide range of frequency starting at a few Hz and going up to tens of GHz, depending on the characteristics to be studied. Recently, many high frequency techniques have been proposed to deeply understand and qualify new materials (especially wafers and substrates) and new devices (active devices such as transistors and passive devices such as inductors). These new techniques rapidly and efficiently define the advantages and the disadvantages of the material/device and precisely define the causes of malfunction or poor quality performance. The result is a shorter time-to-market thanks to less number of iterations between the different steps of final product fabrication.

This paper presents the importance of wideband characterization techniques for fabrication process. Examples are given for new substrate, new device structures and enhancement of existing and mature device structures. The objective is an optimized performance for a LVLP application.

Epitaxially grown Ge and III-V on Si have emerged as a promising candidate for the next generation high performance devices, including high-mobility complementary metal-oxide-semiconductor field-effect transistors. For high-mobility transistors integrated on Si substrates, in particular, managing dislocations and metal-semiconductor contacts has become an important engineering challenge. Herein, we have investigated the impact of threading dislocations and metal-semiconductor interfacial states on Schottky diode characteristics made of Ti and wafer-scale Ge grown on Si. For the purpose of comparison, we have grown epitaxial Ge on Si with two threading dislocation densities: 2x10⁸ and 5x10⁷ cm^-2. The p-type carrier density in the Ge layer is approximately 5x10¹⁶ cm^-3. To prevent Fermi-level pinning, we have also deposited a thin layer of SiO₂ and Al₂O₃ between Ti and Ge with varying thickness, ranging from 5 to 30 nm. With a thin dielectric layer (5 nm), Schottky diodes on two Ge epilayers resulted in an on/off current ratio of approximately 1. This result indicates that there is a significant amount of leakage current. When the dielectric thickness is optimized to 30 nm, we observe that the on/off ratio improves by a factor of 40 and 2000 for SiO₂ and Al₂O₃, respectively. In the case of Al₂O₃, we were able to achieve an ideality factor of 1.67 at 300 K and the reverse leakage current density of ~4.3x10^-10 A/μm² at 300 K. The ideality factor increases to 2.44 at 77 K. This result suggests that the thermionic emission might be the dominant current transport mechanism for Schottky diodes fabricated from Ti and epitaxially grown p-type Ge on Si. However, the slight increase in ideality factor at low temperatures implies a change in the dominant current transport mechanism. In summary, the use of 30-nm-thick Al₂O₃ between Ti and Ge provides improved I-V characteristics for the Schottky diodes. In this presentation, we will further discuss our latest approaches[1] to reduce the dislocations in the Ge epilayer to low 10⁶ cm^-2 level and device characteristics of Schottky diodes fabricated on these low-dislocation-density Ge on Si substrates.

[1] Darin Leonhardt and Sang M. Han, Appl. Phys. Lett. 99, 111911 (2011).

Light emitting devices, namely LEDs and laser diodes, grown on c-plane GaN suffer from large internal electric fields due to discontinuities in spontaneous and piezoelectric polarization effects which cause charge separation between holes and electrons in quantum wells and limits the radiative recombination efficiency. Nonpolar GaN devices, such as in the m-plane {1100}, are free from polarization related electric fields since the polar c-axis is parallel to any heterointerfaces. Semipolar GaN-based devices have reduced electric fields.

Nonpolar and semipolar nitride epitaxial layers have other striking differences from c-plane. Namely, in conventional c-plane GaN heteroepitaxy, there is no shear stress on the easiest slip plane – the (0001) or basal plane and the next easiest slip plane – the prismatic {1100} m-plane. Epitaxy of mismatched layers on nonpolar and semipolar GaN, there are significant shear stresses in the inclined m-planes and on the inclined c-plane. Significant lattice mismatch-related stresses can be relieved by misfit dislocation formation via threading dislocation glide.

In this talk, we present the progress in developing high quality relaxed semipolar templates. The predominant relaxation in semipolar InGaN on GaN or AlGaN on GaN, in orientations such as (1122) or (2021), proceeds via threading dislocation glide on the inclined basal plane, followed in many cases by prismatic slip [1]. Since semipolar GaN has only one (0001) plane, plastic relaxation results in crystallographic tilt which can easily be measured in on-axis x-ray rocking curves or reciprocal space maps and can be directly used to quantify the extent of plastic strain relaxation [2]. The initial misfit stress relaxation occurs by glide of pre-existing threading dislocations [3,4] at a thickness slightly greater than the Matthews-Blakeslee critical thickness; the development of pseudomorphoric InGaN and AlGaN semipolar buffer layers via dislocation strain relaxation [5,6,7]; blue (1122) LDs in relaxed buffer layers [8]; green LEDs on relaxed buffer layers [9].

[1] F. Wu et al., Appl. Phys. Lett 99, 251909 (2011).

[2] E.C. Young et al. Appl. Phys. Express 3, 011004 (2010).

[3] E.C. Young et al. Appl. Phys. Express 3, 111002 (2010).

[4] P.S. Hsu et al., Appl. Phys. Lett. 99, 081912 (2011).

[5] F. Wu et al. J. Appl. Phys. 109, 033505 (2011)

[6] A.E. Romanov et al., J. Appl. Phys. 109, 103522 (2011).

[7] E.C. Young et al. Appl. Phys. Express, 4, 061001 (2011).

[8] P.S. Hsu et al. Appl. Phys. Lett. 100, 021104 (2012).

[9] I. Koslow et al. submitted for publication (2012).

Alloying different semiconductor compounds attracted wide attention, since the materials properties of the resulting semiconductor alloy can be continuously tuned by varying the composition. Hence one can engineer semiconductor materials with, e.g., intentionally designed band gaps, lattice constants, and/or optical properties. This approach possesses a large technical and economical interest, as it is the basis for defining the wavelength of most optoelectronic devices.

In this paper, we present a two-dimensional Ga-Si √3x√3 semiconductor alloy on Si(111) substrates as model system. Using atomically and momentum resolved STM and STS, we demonstrate that the electronic structure, i.e., density of states, band gap, and band structure, is atomically localized and different at Si and Ga atoms. No intermixing and formation of new alloy related electronic properties are observed, as if no alloying ever happened. This unmixed state is discussed in terms of the particular bonding structure of the two-dimensional alloy.