AVS2012 Session EM-TuM: Electrical Testing and Defects in III-V’s

III-V high mobility channel materials are currently drawing attention as possible material candidates for devices to continue scaling of CMOS transistors on the Si platform. Here, construction of high performance high-k MOS gate stacks is the key issue. Such gate stacks are also needed for various gate controlled III-V nanowire and nanodot devices for “Beyond CMOS” applications.

The purpose of this paper is to review the present status of understanding and control of “Fermi level pinning (FLP)” phenomena at III-V metal-gate high-k gate stack interfaces whose atomic level control is vitally important for success of above approaches. FLP at the insulator-semiconductor (I-S) interface deteriorates efficiency and stability of gate control of carriers while FLP at the metal-insulator (M-S) interface deteriorates the control capability of the threshold voltage of the MOSFET.

First, various models on FLP at I-S and M-S interfaces are reviewed, paying attention to chemical trends of pinning at Schottky barriers and MOS capacitors formed on GaAs and other III-V materials. Extremely complicated C-V behavior of ALD high-k dielectric/GaAs MOS capacitors is explained by the authors' disorder induced gap state (DIGS) model [1] where a U-shaped donar-acceptor gap state continuum causes pinning. Importance of the location of the charge neutrality level (CNL) [2] is pointed out for channel material selection, showing superiority of InGaAs over GaAs and others.

Then, various efforts to remove FLP at III-V I-S interfaces by inserting interface passivation layers are reviewed. In particular, authors' efforts to realize pinning-free high-k MOS interfaces on GaAs and InGaAs, using the silicon interface control layer (Si ICL) are described. Here, the Si ICL is an MBE-grown ultrathin Si interlayer which is proposed first by the authors [2,3] and now extended　to construction of high-k MOS gate stacks. The structure has been investigated by XPS, contactless C-V and STM/STS methods and by ex-situ PL and MOS C-V measurements [4-7].

Finally, the FLP issue at metal-high-k Schottky interfaces is briefly discussed.

[1]H. Hasegawa and H. Ohno, J. Vac. Sci.Technol, B4, 1130 (1986) [2]H. Hasegawa, M. Akazawa et al J. Vac. Sci. Technol. B 7, 870 (1989).[3]H. Hasegawa, M. Akazawa, et alJpn. J. Appl. Phys.. 27, L2265 (1988) [4]M. Akazawa and H. Hasegawa, J. Vac. Sci. Technol. B25, 1481(2007)[5]M. Akazawa and H. Hasegawa, J. Vac. Sci. Technol. B26,(2008)1569 [6]M. Akazawa, A.Domanowska, B. Adamowicz and H. Hasegawa, J. Vac. Sci. Technol. B27, 2028(2009) [7]M. Akazawa and H. Hasegawa, Appl. Surf. Sci., 256, 5708(2010)

Anomalous frequency dispersion in accumulation is a commonly observed feature in experimental capacitance-voltage (C-V) characteristics of III-V metal-oxide-semiconductor (MOS) devices. Different models have been proposed to explain the origin of this frequency dispersion. One model attributes this dispersion to tunneling of the carriers into a disordered region caused by oxidation of the III-V substrate which is close to the interface between the III-V substrate and an insulator.^1,2 Another model attributes this dispersion to border traps located inside the high-k dielectric.^3,4 In this work, we use both HfO₂ and Al₂O₃ with several interface treatments to differentiate between these two models.

MOS capacitors are fabricated on As-decapped n-In_0.53G_0.47As and n-GaAs substrates with either atomic layer deposited (ALD) HfO₂ or Al₂O₃ dielectrics. An As-cap initially grown on the n-In_0.53G_0.47As surface to avoid spurious oxidation is thermally desorbed to leave a pristine surface. ALD HfO₂ and Al₂O₃ is then deposited onto substrates prepared with several conditions: (1) in situ on the oxide free surface, (2) ex situ with a 10% ammonium sulfide and immediate transfer to ALD (<3 min exposure to air), (3) ex situ with a 10% ammonium sulfide treatment and ~30 min exposure to air prior to ALD. Companion GaAs samples receive similar ex situ ammonium sulfide treatments, air exposure times and ALD dielectrics for comparison. A detailed analysis of the effect of the different disordered region thicknesses and different dielectrics on the accumulation frequency dispersion and interface trap density (D_it) distribution will be presented. Correlation of electrical results to X-ray photoelectron spectroscopy (XPS) analysis will also be presented.

This work is sponsored by SRC FCRP Materials Structures and Devices Center and the National Science Foundation under ECCS Award No. 0925844.

1] H. Hasegawa and T. Sawada, IEEE Trans. Electron Devices 27(6), 1055 (1980).

[2] A. M. Sonnet, C. L. Hinkle, H. Dawei, G. Bersuker, and E. M. Vogel, IEEE Trans. Electron Devices, 57, 2599 (2010).

[3] Y. Yuan, L. Q. Wang, B. Yu, B. H. Shin, J. Ahn, P. C. McIntyre, P. M. Asbeck, M. J. W. Rodwell, and Y. Taur, IEEE Electron Device Lett.32 (4), 485 (2011).

[4] E. J. Kim, L. Wang, P. M. Asbeck, K. C. Saraswat, and P. C. McIntyre, Appl. Phys. Lett.96 (1), 012906 (2010).

GaAs is a promising channel material for sub-20nm logic MOSFET due to high electron mobility. However the instability of its native oxide is considered to generate high density of interface states that can induce Fermi level pinning and frequency dispersion in capacitance-voltage (C-V) curve. Although a variety of dielectric materials have been investigated over the past 4 decades to improve interface properties, a few positive results have been reported: Ga₂O₃ (Gd₂O₃) grown by molecular beam epitaxy (MBE) and Al₂O₃ and HfO₂ grown by atomic layer deposition (ALD). In this study, n-type GaAs MOSCAP’s were fabricated with ALD SiO₂, Al₂O₃, La₂O₃, and HfO₂, and measurements of C-V hysteresis, flatband voltage shift (ΔV_fb), and frequency dispersion were performed to investigate the dependence of electrical properties on dielectric materials and to find dielectrics suitable for a stable MOSCAP operation.

Only HfO₂ revealed good electrical characteristics with a C-V hysteresis of < 80 mV and ΔV_fb of 40 mV under constant stress time and voltage, while SiO₂, Al₂O₃, and La₂O₃ showed significantly degraded characteristics with a C-V hysteresis of > 700mV hysteresis and ΔV_fb of 200mV. But even though a single HfO₂ dielectric layer had good electrical characteristics, the stacked HfO₂/SiO₂ dielectric layer on GaAs showed the degraded characteristics like a single SiO₂ layer, indicating that the electrical characteristics were mainly dependent not on bulk properties but on the interface properties with GaAs. X-ray photoelectron spectroscopy (XPS) analysis revealed that SiO₂, Al₂O₃, and La₂O₃ dielectrics produced more elemental As (As⁰) than HfO₂ did at the interface. In addition, for SiO₂, Al₂O₃ and La₂O₃ dielectrics, As were detected on the top surface of dielectrics by Auger electron spectroscopy (AES) measurement, implicating that the origin of degradation was related with the amount of elemental As, which might diffuse out and induce vacancy defects during subsequent annealing process, at the interface.

Frequency dispersion characteristics in a C-V measurement were also compared. HfO₂ showed huge frequency dispersion of about 280 % (ΔC_1kHz~1MHz/C_1MHz) while SiO₂, Al₂O₃, and La₂O₃ resulted in the relatively small dispersion of about 50% unlike the C-V hysteresis tendency. However, HfO₂ on thin SiO₂ led to small dispersion similar to SiO₂. Frequency dispersion was strongly correlated with the interface state density (D_it). Therefore, we can conclude that both hysteresis and frequency dispersion in a C-V measurement are dependent on the interface properties of dielectrics, especially the amount of elemental As and Dit level, respectively.

In this work synchrotron radiation based hard x-ray photoelectron spectroscopy (HAXPES) measurements have been used to study the intrinsic electronic properties of high-k dielectric metal oxide semiconductor (MOS) structures on Si, GaAs and InGaAs substrates. The MOS structures were prepared with both high (Ni) and low (Al) workfunction metal layers 5nm thick on both n and p doped semiconductor substrates. CV and IV measurements were also performed on an identical sample set where the top metal contact was 160 nm thick to facilitate electrical measurements, and Ni was replaced with Ni/Au, 70/90 nm thick, respectively. The 4150 eV photon energy used in the HAXPES measurements gave a photoemission sampling depth of ~15 nm ensuring that signals were simultaneously detected from the substrate, the 8 nm thick dielectric layers as well as the top metal contact. The binding energy of core levels in photoemission are referenced with respect to the Fermi level, therefore changes in the binding energy of a particular core level reflect differences in the position of the Fermi level in the semiconductor band gap. For the MOS structures fabricated using SiO₂/Si, changes in the Fermi level positions and differences in the potential drops across the dielectric layers have been directly correlated with the metal workfunction differences observed in the CV and GV measurements. The MOS structures on ammonium sulphide passivated n (Si - 5x10¹⁷ cm^-3) and p (Zn - 5x10¹⁷ cm^-3) doped GaAs substrates were fabricated by the atomic layer deposition (ALD) of 8 nm thick Al₂O₃ dielectric layers. A binding energy difference of 0.6 eV was measured between the GaAs core levels of the n and p doped substrates, independent of metal work function indicating that the Al₂O₃/GaAs interface is strongly pinned. Lattice matched 0.2 μm thick In_0.53Ga_0.47As layers, with both n and p doping (~4x10¹⁷ cm^-3), were grown by MOCVD on InP n⁺ and p⁺ substrates, respectively. Al₂O₃ dielectric layers 8 nm thick were then deposited ex-situ by ALD on the native oxide and ammonium sulphide treated InGaAs surfaces. Binding energy measurements for the core levels of native oxide covered n-type doped InGaAs substrates with no metal cap were found to be consistently (~0.3 eV) higher than p-type samples reflecting the fact that the Fermi level is in a different position in the band gap. Deposition of the metals with different workfunctions resulted in limited movement of the Fermi level, indicating the partially pinned nature of the InGaAs/Al₂O₃ interface. Corresponding changes in the potential across the dielectric layer were also measured.