Development of p-type MOSFETs using new materials is an important goal to provide a further scaling of CMOS circuits. Although Ge is still considered as a main candidate for novel p-channels due to its superior bulk transport properties, recent progress in strained III-Sb channels and MOS technologies makes it a good competitor in particular for deeply scaled devices. The materials parameters affecting MOSFET’s figures-of-merit are reviewed with the emphasis on strain in quantum wells (QWs), effective mass, density of states and mobility.

Progress in development of materials for III-Sb channels is reported. Optimization of MBE growth of metamorphic buffers and GaSb on lattice-mismatched GaAs substrates has resulted in “step-flow” growth mode of GaSb with monolayer-high steps on the surface, ~10⁷cm^-2 dislocation density and bulk hole mobility 860cm²/Vs. Optimization of strain in QWs provided the highest Hall mobility of 1020 cm²/Vs at sheet hole density of 1.3x10¹²/cm² obtained for In_0.36Ga_0.64Sb with compressive strain of 1.8%. Hole mobility in QW channel was benchmarked against the thickness of top semiconductor AlGaSb barrier. The effect of interface-related scattering hole mobility in the channel was found to be significantly less than e.g. for n-InGaAs, that might be due to stronger localization of holes in QWs.

Two approaches to fabricate high-quality III-Sb/high-k interface were studied: all in-situ Al₂O₃ or HfO₂ gate oxides, and ex-situ atomic layer deposited (ALD) Al₂O₃ with InAs top semiconductor capping layer. Interface with in-situ MBE gate oxides was found to improve with in-situ deposited a-Si interface passivation layer (IPL). Interfaces with better thermal stability, reduced interface trap density and hysteresis were observed on both n- and p- type GaSb MOSCaps with the IPL. P-type MOSFETs with HfO₂ showed a maximum drain current of 23 mA/mm for a 3μm gate length. Use of a-Si IPL has also resulted in a significant (over an order of magnitude) reduction of the hole density in QWs and corresponding negative flat band voltage shift and drop of mobility which becomes remote Coulomb scattering-limited. An interface with ALD Al₂O₃ was improved by a thin 2nm interface layer of InAs which was treated with HCl or(NH₄)₂S immediately prior to ALD process. Optimized annealing further improved the C-V characteristics, reduced interface trap density down to 10¹² cm^-2eV^-1, leakage current and MOSFET subthreshold slope down to 200 mV/dec. Increasing annealing temperature to and above 450^oC drastically degraded C-V characteristics due to low thermal budget of antimonides.

Due to the high two-dimensional electron gas (2-DEG) density, AlGaN/GaN high electron mob­­­i­l­i­t­­y transistors (HEMTS) are recognized as key devices for high power and low noi­s­e ap­p­l­­ic­a­tions. However, the associated large gate leakage current degrades the performance of AlGaN­ HE­M­­Ts. In order to solve this problem, MOS-HEMTs have been developed, in which the incorporation of a high-k gate di­e­l­e­ctric ­l­a­yer can overcome the drawbacks.

In this work, the native and treated Al_0.25Ga_0.75N surface chemical states and structure of were studied by x-ray photoele­c­t­ron spectroscopy (XPS), ion scattering spectroscopy (ISS) and l­o­w ene­r­gy electron diffraction. Different chemical treatment processes including (NH₄)OH, (NH₄)₂S and HF were studied, followed by atomic layer deposition (ALD) Al₂O₃ layers on Al_0.25Ga_0.75N . T­he oxidation states of the Al_0.25Ga_0.75Ninterface and Al₂O₃ deposition process were st­udied b­y in-situ XPS analysis. In addition, ex-situ atomic force microscopy (AFM) was used to obs­e­rve the surf­­a­ce topography before and after the Al₂O₃ deposition. According to the XPS results, it is found that chemical treatments could remove the native Al₂O₃ but were not effective to eliminate the Ga oxide, and the growth rate of Al₂O₃ is low on the native and treated Al_0.25Ga_0.75N samples. The AFM images show that there are many pin holes in the surface of Al_0.25Ga_0.75N. Studies of HfO₂ deposition will also be presented.

This work is supported by the AOARD under AFOSR Grant No. FA2386-11-1-4077

Thin silicon nitride films have long been desirable for various applications. Suggested uses range from surface and interface passivation to ultra-thin dielectric layers. Traditional deposition techniques are low pressure chemical vapor deposition (LPCVD) and plasma enhanced chemical vapor deposition (PECVD). High quality LPCVD films require high processing temperatures, and PECVD exposes the substrate to damaging plasma and electric potentials. While both techniques are suitable for many applications, there are some instances where both processes are too harsh.

In this paper, we report the growth of silicon nitride using a remote nitrogen radical generator system. Growth temperatures range from room temperature to 400 °C,and growth time is varied from two minutes to one hour. Film composition is analyzed using x-ray photoelectron spectroscopy (XPS) and morphology is checked using atomic force microscopy. Results indicate that surface nitrogen saturation can be reached at both low temperatures and short exposure times,and that the reaction is self limiting, terminating at one monolayer. Film thickness is approximately one Angstrom, as determined by XPS. Results for silicon and III-V passivation will be discussed.

We would like to thank Toshiba Mitsubishi-Electric Industrial Systems Corporation for providing the nitridation system used in this study.

It has always been harder to make FETs from GaAs than Si, because of ‘Fermi level pinning’ and the difficulty of passivating its surfaces. These issues were discussed by Spicer et al [1] in the ‘unified defect model’ and Hasegawa [2] is his ‘Disorder Induced Gap states’ model. Since 1997 it was possible to make inverted GaAs MOSFETs using the epitaxial Gadolinium gallium oxide [3]. The main impetuous now is to use atomic layer deposition (ALD) to make scalable FETs [4], as recently achieved by Intel [5]. The obvious question is why (In)GaAs is much harder to passivate than Si. The early answer was its poor native oxide. But since the advent of good ALD HfO2 or Al2O3 oxides on Si, this answer is deficient, as they should also work on GaAs [6]. The underlying reason for defects is not stress, it must be chemical. I show that it arises from the polar bonding of GaAs [7], and a driving force to keep the surface Fermi level in a gap. The electron counting rule of Pashley [8] that describes surface reconstructions is shown to be a variant of auto-compensation, and it works more generally [9]. It leads to a continuous generation of defects if it is not satisfied. So the answer is to deposit oxide layers that meet this rule, and also to break any surface reconstructions that may lead to As-As dimers [9]. Diffusion barriers are also crucial to a good passivant, on GaAs or on Ge .

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2. H Hasegawa, et al, J Vac Sci Technol B 5 1097 (1987)

3. M Hong et al, Science 283 1897 (1997)

4. P D Ye et al, App Phys Lett 83 180 (2003)

5. M Radosavljevic, et al, Tech Digest IEDM (2009) p13.1

6. C Hinkle, et al, Curr Opin Solid State Mat Sci 15 188 (2011)

7. W Harrison, J Vac Sci Technol 16 1492 (1979)

8. M D Pashley, Phys Rev B 40 10481 (1989)

9. J Robertson, L Lin, App Phys Letts 99 222906 (2011); 98 082903 (2011)