Continued scaling in the semiconductor industry provides new challenges for critical etch applications in front-end logic and memory devices. As device sizes shrink, control of Shallow Trench Isolation (STI) features to create active area islands become more important. Typical logic STI performance metrics for a 300mm wafer include trench angle, trench depth and iso-dense depth loading and their corresponding within-wafer uniformity. In addition to these metrics, memory STI application includes a challenging requirement for intra-cell depth loading that arises due to within-feature variation of the space critical dimensions (CD) in the dense feature array. These stringent profile control requirements are typically met by operating halogen-based Transformer Coupled Plasma (TCP™) in the mid-pressure operating regime.

This paper will discuss the semi-empirical feature scale model of STI etch in HBr plasma to address iso-dense and intra-cell trench depth loading for an etch stack representative of memory STI features. Plasma diagnostics and reactor-level models are implemented to characterize the HBr plasma produced in the TCP configuration process chamber. Kinetic parameters in the model are constrained by matching simulated feature profiles with those experimentally obtained at various process conditions that are a subset of the process space of interest. The feature scale model is quantitatively calibrated to the experimental profiles and validated for prediction within the process space. The validated profile simulator is used to identify reactor-level process knobs that minimize iso-dense and intra-cell depth loading. The advantages of calibrated process-specific profile simulation in enabling efficient exploration of parameter space during process development and future challenges facing STI trench depth etch will be discussed.

Uniformity requirements (both etch rate and critical dimensions) for plasma etching of very small features (< 32 nm) are more stringent than ever. One particular challenge is minimizing feature distortion due to plasma induced damage. If the feature aspect ratio is high, via-like features in dielectric materials may physically twist/turn due to the stochastic nature of fluxes entering the feature as the size of the opening shrinks [1]. Limited quantity of polymer on the sidewalls exaggerates this feature distortion. Pulsed plasma operation is a promising approach to improve uniformity while reducing feature distortion [2]. Although pulsing of both capacitively and inductively coupled plasma (CCP/ICP) sources has been investigated before, novel pulsing schemes such as synchronously pulsed ICPs allow for expanded operating regime for damage-free etching of nanoscale features.

In this paper, pulsed and continuous plasma operation of an ICP reactor in electronegative gas mixtures will be discussed using results from a computational investigation. Earlier investigations [3] have linked a 2-dimensional plasma equipment model (HPEM) to a Monte Carlo feature profile model to assess the consequences of pulsed plasma operation on etching. Long computational times restricted the range of conditions that could be investigated, e.g. more complex chemistries or lower pulse frequencies. We have addressed this constraint by using a global plasma model (Zephyr) combined with analytical expressions for behavior in the sheath. The global plasma model is based on the methods described by Meeks et al [4]. This model calculates all the species (neutrals, ions and electrons) concentrations and their temperatures using time-dependent conservation equations, including both gas and surface reactions. The impact of different surface materials on plasma chemistry is also captured. The global plasma model is validated using more detailed 2-dimensional plasma modeling and experimental diagnostic results for simple chemistries (Ar, O₂). The validated model is then applied to pulsed plasmas of highly electronegative chemistries used for silicon etching (Cl₂ and HBr based). Results will be discussed for impact of pulse characteristics such as duty cycle, pulsing frequency, and phase lag between source and bias pulses on etching in an ICP chamber.

¹ M. Wang and M.J. Kushner, J. Appl. Phys. 107, 023308 (2010).

² S. Banna, et al., Trans. Plasma Sci. 37, 1730 (2009).

³ A. Agarwal et al, J. Appl. Phys. 106, 103305 (2009).

⁴ E. Meeks, H.K. Moffat, J.F. Grcar and R.J. Kee, SAND96-8218 (1996)

Graphene is a two-dimensional hexagonal lattice of carbon atoms with the thickness of one or a few atomic layers. Due to its material stability and strength, absence of defects, and unique electronic band-structure, graphene holds considerable promise for a number of applications in nanoscale electronics, optoelectronics, and mechanics in addition to showing fundamental interest in condensed matter physics. Many potential applications, such as graphene-based high-speed field-effect transistors, require graphene to be patterned to the nanoscale and, in some cases, graphene needs to be etched precisely with atomic layer precision. However, through the conventional reactive ion etching, it is difficult to control the etch depth precisely due to the fluctuation of the etch process in addition to the damage to the graphene by the reactive ions.

In this study, to overcome the above problems, the atomic layer etching technique (ALET) has been applied in the etching of graphene, and the etch characteristics of graphene by ALET were investigated. For the adsorption gas, O₂ was used, and Ar neutral beam was used for the desorption of the adsorbed compound. For the few layer graphene deposited on the SiO₂ (300 nm)/ Si substrate, the monolayer etching condition of graphene was observed by supplying O₂ radical at a pressure higher than the critical pressure during the adsorption step and by supplying an Ar beam at a dose higher than the critical dose. Self-limited etching of graphene could be obtained using O₂ radical ALET.

Magnetoresistive Random Access Memories (MRAM) is of great interest since they combine the best characteristics of FLASH, SRAM and DRAM memories: non-volatility, low voltage operation, unlimited read and write endurance, fast read and write operation. One of the key parameters for M-RAM technology development is the etching of the Magnetic Tunnelling Junction (MTJ). Today, one of the main methods used for MRAM patterning is based on a pure sputtering dual Ion Beam Etching (IBE). However, IBE technique shows some technological limitations that increases the difficulty of MRAM device manufacturing. Indeed, it has low throughput and cannot be used to pattern very dense structures because of shadowing effects., The process can lead to magnetic materials redeposition on the pattern sidewalls that can short-circuit the dielectric tunnel junction. In this paper, we propose to develop plasma etching technologies to pattern complex stacks of MRAM devices as an alternative to IBE process, improving the manufacturability of MRAM devices.

The aim of this work is to investigate a full RIE process for the patterning of Thermally Assisted MRAM (TA-MRAM) dots in ICP reactors (Decoupled Plasma Source from AMAT).

We propose to investigate innovative plasma chemistries (without O₂, Cl₂ to avoid corrosion) to etch the magnetic materials composing the MTJ junction. CO/NH₃ plasmas assisted by temperature could be very promising plasma chemistries to form volatile metal-carbonyl etch by products and avoid redeposition on the pattern sidewalls.

Optical Emission spectroscopy and reflectometry is used to monitor the plasma process. The etching profile, critical dimensions (CD) and possible redeposition on sidewalls are analysed using Scanning Electron Microscopy (SEM), and Focused Ion Beam devices (FIB-SEM, FIB-TEM). The nature of non-volatile by-products re-deposition is studied using X-Ray Photoelectron Spectroscopy.