Porous dielectric materials offer lower capacitances that reduce RC time delays in integrated circuits. Typical low-k materials include SiOCH – silicon dioxide with carbon groups, principally CH₃, lining the pores. Fluorocarbon plasmas are often used to etch low-k materials. These processes leave a fluorocarbon polymer on the low-k surface that must be removed. This is often done with oxygen containing plasmas. With porosities as high as 0.5, pores open to the surface and which are internally connected provide pathways for reactive species to enter into the porous network. Reactions during plasma cleaning of, for example, O atoms with the CH_x groups, can increase the k value of the material by removing C atoms. To maintain the low-k value, cleaning the CF_x polymer and sealing of the surface must be performed without significantly altering the SiOCH material properties, and not removing the CH_x groups. Plasma cleaning with He/H₂ mixtures is capable of removing these CF_x residues without harming the underlying low-k surface and can also strip off the hydrocarbone photoresist (PR) mask.

In this talk, we discuss results from modeling of the plasma cleaning and sealing of porous SiOCH in sequentially applied He/H₂ and Ar/NH₃ plasmas. The HPEM (Hybrid Plasma Equipment Module) was employed to obtain the ion energy and angle distributions of reactive fluxes from inductively coupled plasmas. These are used as input to the MCFPM (Monte Carlo Feature Profile Module) with which profiles of the low-k materials after the plasma exposures are predicted.

We found that hot hydrogen atoms can remove the CF_x polymer, generating mainly HF and fluorohydrocarbons such as CHF₂. These hot H-atoms can simultaneously remove H from the surface resident CH₃ groups thereby activating the SiOCH surface by creating C dangling bonds. He ions are also effective at breaking Si-O bonds creating dangling while also removing H-atoms from CH₃ group, both of which activate the SiOCH surface. Unlike O₂ plasma cleaning, the He/H₂ clean creates more reactive CH_x (x = 1,2) sites without significantly damaging the substrate. Following the He/H₂ plasma cleaning, NH₃ plasma treatment seals the pores by NH_x (x=1,2 and 3) species passivating previously produced dangling bonds, forming Si-N and C-N bonds.[1] Initial results indicate that combined He/H₂ and Ar/NH₃ plasma treatment of SiOCH with pores having radii of 0.8 nm can seal nearly 100% of the surface pores.

* Work supported by Semiconductor Research Corp.

[1] A. M. Urbanowicz, M. R. Baklanov, J. Heijlen, Y. Travaly, and A. Cockburn, Electrochem. Solid-State Lett. 10, G76 (2007).

There has been much interest recently in porous oxycarbosilane (POCS)-based materials as the interconnect layer dielectric (ILD) in back-end-of-line (BEOL) manufacturing due to their superior mechanical properties compared to conventional porous SiCOH at equivalent porosity and dielectric constant. [1-4] While it is well known that plasma etching and ashing processes can cause significant damage to porous ultra-low k dielectric materials in general, little has been reported about the effect of plasma damage to POCS as the ILD material. In this work, we discuss the effect of plasma etching and ashing processes on POCS during the fabrication of single and dual damascene structures for BEOL integration. We used TEM-EELS to quantify chemical composition changes at the top, bottom, and sidewalls of POCS trenches after each plasma etching and ashing step. After plasma processing, POCS structures undergo extensive plasma damage such as pitting, microtrenching, and the generation of trench bottom roughness. Opening of the cap layer exacerbates these etch damage features. Damage is reduced by increasing the neutral-to-ion ratio of the gas discharge in the ULK trench etch and eliminating O₂ from the ashing process. The use of vapor phase silylation between etch process steps is also shown to repair plasma-damaged POCS. However, we show that the most significant improvement to post-plasma damage occurred by reducing the pore size of the starting POCS material while maintaining comparable porosity, i.e. dielectric constant.

[1] W. Volksen, et al., Chem. Rev. 110, 56 (2010).

[2] G. Dubois, et al., J. Of Sol-Gel Science and Technology 48, 187 (2008).

[3] G. Dubois, et al., in Dielectric Films for Advanced Microelectronics, edited by M. Baklanov, et al., (Wiley, New York, 2007), p. 33.

Reactive Ion Etch [RIE] of Silicon Nitride films, utilized primarily as spacers, hard masks or etch stop layers [ESLs], is pervasive throughout logic and flash microelectronics fabrication processes. While the most critical RIE-related specifications vary widely depending on the specific application and photolayer, contact level liner/ESL removal is among the most challenging. This application ideally requires high etch selectivities to multiple material types [including NiSi, SiO₂, Si, and Si_xGe_y] at the bottom of a high aspect ratio feature where etch stop marginality in a polymer rich regime can impact opens yield. Furthermore, relying on high radical density, low ion energy, primarily chemical etch processes utilized for Si_xN_y type spacer applications often lack profile control where sidewall bowing can result in metallization related yield fallout.

This work characterizes a new contact RIE process developed for 28nm and beyond technology nodes. Reported is the successful integration of an ultra high selectivity Si_xN_y liner removal process [> 40:1 in hole selectivity for Si_xN_y : Si]. Cross-sectional characterization of contact profile and in hole selectivity data will be provided. High Opens/Shorts yield [equal or better than baseline] as determined by voltage contrast metrology and inline E-Test will be shown. In addition, a 10x reduction in gate leakage will be shown based in-line E-Test attributable to reduced active area Si loss/recess.

Non-volatile phase change based memory has recently garnered significant interest due to its potential for scalability beyond that of conventional DRAM and Flash memory technologies.[1] However, multiple etch challenges exist in the fabrication of robust PCM devices and not all have been thoroughly discussed and/or researched. For instance, patterning of the novel phase change material without causing material modification and performance degradation is a well known issue and has been reviewed in the past.[2,3,4] On the other hand, the ability to fabricate robust and uniform sublithographic contacts (to the phase change material) is rarely discussed from an etch perspective. In this presentation, this latter issue is explored in detail and a lithographically independent etch process scheme with the capability of yielding sub-35nm vias is presented. Critical factors such as oxide and nitride etch selectivity, taper angle and etch stop phenomenon are all reviewed. Lastly, the application of this method for logic applications such as gate contacts and BEOL via patterning will also be discussed with a focus on the ultimate scaling limitations of this process.

[1] Y.C. Chen, C.T. Rettner, S. Raoux et al., IEDM Tech. Dig., p. S30P3, 2006.

[2] P. Petruzza, Paper PS-MoA4, AVS 54th International Symposium, 2007

[3] E. A. Joseph, T. D. Happ, S.-H. Chen, S. Raoux, et al., Symp. VLSI-Technology Systems and Applications, 2008. pg 142-143, 2008

[4] E. A. Joseph, S. Raoux, J. L. Jordan-Sweet, D. Miller, H-Yu Cheng, A. Schrott, C-F. Chen, R. Dasaka, B. Shelby, Y. Zhang, C. Lam, J. Washington, G. Lucovsky and M. Paesler, Paper PS1-ThM11, AVS 56th International Symposium, 2009