Moore’s Law has been the driver for semiconductor integrated circuits over more than 40 years. Relentless scaling of dimensions switching provided increasing functionality and performance, resulting in leading edge single chips today that incorporate more than 1 Billion transistors.

All attempts on predicting the end of Moore’s Law have been futile – innovations have always allowed continued scaling at reduced cost. However, while Moore’s Law appears to be a continuous curve, we rarely reflect on the underlying changes that had to occur to enable this rate of progress. These changes comprised device architecture, the introduction of new materials and break-through processes.

Since Moore’s Law describes a learning curve for which cost reduction is central, process simplicity frequently won out over performance advantages if the latter came at high cost. Self-aligned implanted poly-gate over the early metal gate structures is a prime example. Aggressive reduction in the cost per function also provided performance benefits: Smaller transistors switched faster and used less power to do so – truly a win-win situation.

Key innovations along this path were:

· The switch from thermal diffusion doping to implant

· The introduction of CMP, which was key in increasing the number of metal layers that could be integrated.

· The introduction of high-k dielectrics in conjunction with metal gates which addressed the critical gate leakage problem and will allow the introduction of new and better performing channel materials.

Compared to the past, the future will require even more innovation along three potential directions:

· Continuous improvements of current methodologies along existing technologies, consisting of solid engineering and hard work.

Innovations pursued in this category are: highly regular layouts, new channel materials in conjunction with modified hi-k/MG (yet planar) structures.

· Significant changes to traditional device structures and processes.

An example of innovations pursued in this category is the FinFET, which presents significant challenges in materials and processes that must be resolved before introduction into the manufacturing cycle.

· Radical new structures and approaches resulting in major deviation from today’s mainstream technologies.

An example is new fundamental circuit components such as the Memristor or new approaches available if considering device operations at cryogenic temperatures (which may be feasible for server farms), allowing the exploration of concepts such as superinsulators.

This presentation will highlight the state-of-the-art in process technology and discuss challenges that require attention and timely solutions.

ZnO based oxide semiconductor is a promising material for thin film transistor which has transparent, high electric mobility, and the advantage of low temperature process. Several kinds of ZnO based oxide semiconductors (InZnO, GaInZnO, HfInZnO, etc.) have been adapted to the active material of thin film transistor. However most of ZnO based oxide semiconductors have very sensitive property to ambient environment. It is essential to prevent the penetration of moisture into ZnO based oxide thin film transistor (TFT). In the purpose of preventing moisture penetration and/or protecting damage from TFT processes, SiN_x or SiO₂ passivation layer is used frequently.

In this study, we investigated the interface reactions between amorphous HfInZnO (Hf:In:Zn= 10:35:55, 40nm thickness) oxide semiconductor active layer and the passivation layer of SiN_x or SiO₂ (20 nm thickness). TEM, XPS and SIMS were used to investigate the interface reactions such as atomic diffusion, reduction of HfInZnO, chemical state, microstructure.

According to experimental results, a SiO₂ phase and Indium metallic state were observed at the interface between SiNx and HfInZnO active layer. On the other hand, there was not observed Indium metallic state at the interfaces between SiO₂ and HaInZnO layers. In the case of SiN_x passivation, it is considered that some Si took oxygen from Indium oxide in HfInZnO and oxidized to SiO₂. And some of Indium oxide reduced to metallic Indium at the interface. Indium diffusions from HfInZnO layers into passivation layers were observed at the both of SiNx and SiO₂ samples. In the case of SiN_x passivation, it was a little bit higher diffusion than that of SiO₂ passivation. The low binding energy shift was observed at the Zn_2p XPS spectra at the both samples. However, there was no distinct difference at the Hf_4d spectra.

If there is metallic Indium between passivation and HfInZnO active layers, the metallic Indium may influence the conductance of active layer. The threshold voltage (V_th) shift of thin film transistor (TFT) could be affected by the change of conductance of active layer.

We observed that the V_th negative shift of the TFT used SiN_x passivation was higher than that of SiO₂ passivation. It may be due to the existence of metallic Indium at the interface.

In this report, it will be described the relationships between interface reactions and the property of HfInZnO oxide TFT in detail.

There has been much attention paid recently to the lowering of the threshold voltage (V_t) that is accomplished by including an additional ultrathin (~5-10 Å) oxide layer in the high-k/metal gate metal oxide semiconductor field effect transistor (MOSFET) gate stack. We have investigated the TiN/HfO₂/La₂O₃/SiO₂/p-Si stack, where the La₂O₃ layer is the so-called V_t-shift layer. For several variations of this stack, where both the thickness and the position of the La₂O₃ layer were systematically varied, we measured two quantities directly related to the V_t, the flatband voltage (V_fb) and the Si band bending. The V_fb was measured using capacitance-voltage (C-V) measurements on stacks with 500 Å TiN layers, and the Si band bending was measured on sister wafers with 30 Å TiN layers. For a set of samples where the thickness of the La₂O₃ between the HfO₂ and SiO₂ layers was varied, we observed that the V_fb and Si band bending both become more negative as the thickness of the La₂O₃ was increased. For a set of samples where position of the La₂O₃ within the HfO₂ layer was varied, we observed that the V_fb and Si band bending became less negative as the amount of HfO₂ between the La₂O₃ and the SiO₂ was increased. These observations support the proposition that there is a dipole at the La₂O₃/SiO₂ interface which affects the Si band bending, as has been reported in the literature.^1,2 We have also observed that there is a difference in the V_fb and Si band bending in TiN/HfO₂/La₂O₃/SiO₂/p-Si stacks with thermally grown and chemically grown SiO₂ layers. Results of this study as well as one where the thickness of thermally grown SiO₂ layers was varied will be presented, and it implications on the theory of the interface dipole with be discussed.

1. K. Kita, et al., Appl. Phys. Lett, 94, 132902 (2009).

2. P.D. Kirsch, et al., Appl. Phys. Lett., 92, 092901 (2008).

Electrochemical deposition of Cu for interconnect metallization traditionally uses Physical Vapor Deposition (PVD) of a Cu seed layer on top of a PVD Ta/TaN barrier to conduct the current. However, the limitations of PVD in respect of step coverage compromise its use in future technology nodes. Atomic Layer Deposition (ALD) for barrier deposition combined with seedless Cu electroplating is one of the metallization routes explored for sub-25 nm line widths. However, compatibility with seedless electroplating seriously limits the choice of materials. Among the different candidates, Ru-based layers have been identified as very promising.

We report the growth and scalability of Ru films by plasma-enhanced ALD (PE-ALD) from MethylCyclopentadienylPyrrolylRuthenium (MeCpPyRu) and N₂/NH₃ plasma. The layers were deposited using a 300 mm showerhead type reactor (AMAT) with direct plasma capability. The substrate temperature during deposition was 330C. The Ru growth per cycle was 0.04 nm. As substrates we used Si wafers with 100-300 nm SiO₂ on which a thin TaN or TiN layer was deposited by ALD or PVD.

The metal nitride is needed as a growth enabler since Rutherford backscattering spectrometry (RBS) showed that only 1E14 Ru atoms/cm², i.e. less than a monolayer, were deposited on SiO₂ after 120 PE-ALD cycles. The minimal thickness of the metal nitride to enable Ru growth has been determined to be as low as 0.7-0.8 nm which is promising for scaling. Growth studies on scaled and thick ALD TiN or TaN still showed a limited growth inhibition during the first 40 cycles followed by a linear growth behavior. Static time-of-flight secondary ion mass spectroscopy (TOFSIMS) suggests Ru layer closure for a film thickness around 2 nm.

Atomic force microscopy revealed that the root mean square roughness values were below 0.4 nm for film thicknesses up to 20 nm. X-ray diffraction showed that the Ru layers have a hexagonal structure. The density of the Ru layer was 11.75 g/cm³ as derived from X-ray reflectivity and RBS. Elastic recoil detection analysis and TOFSIMS indicate that the N, O, C-levels in the bulk Ru layers were << 1%. Surface analysis by static TOFSIMS showed the presence of organic contamination identified as MeCp ligands from the Ru precursor. In contrast, the Pyrrolyl ligand was not observed. A post deposition thermal treatment of the Ru film removes the ligand organic contamination. The impact of this surface contamination on the seedless Cu electroplating efficiency will be discussed. Finally, the step coverage of TiN/Ru and TaN/Ru stacks in narrow lines (65-15 nm width) was evaluated by transmission electron microscopy.