AVS2010 Session PS+MN-WeM: Plasma Processing for 3D Integration, TSV, and MEMS

Wednesday, October 20, 2010 8:00 AM in Room Galisteo

Wednesday Morning

Time Period WeM Sessions | Abstract Timeline | Topic PS Sessions | Time Periods | Topics | AVS2010 Schedule

Start Invited? Item
8:00 AM PS+MN-WeM-1 High Etch Rate of TSV using by Ultra Self-Confined VHF-CCP
Yasuhiro Morikawa, Manabu Yoshii, Naoki Mizutani, Koukou Suu (ULVAC, Inc., Japan)
Thru silicon via (TSV) etch process for deep and high-aspect ratio structure has been studied thoroughly for applications such as MEMS devices. Recently, TSV used in 3D-LSI devices, the via diameter and depth would be several tens of microns, and, the package for CMOS image sensors using TSV may have via diameters and depths up to 100 microns. A diameter of above 50um account for 50 % of TSVs. Therefore, development of high etch rate about 50um via is very important for realizing these applications. In this study, a large via size of 50 um etching in a low-pressure process was focused by using very high frequency capacitive coupled plasma (VHF –CCP) with an ultra self-confined system. This plasma system is simple parallel plate CCP. And the cathode has a structure designed to minimize the stray capacitance (Cs) and impedance (L) to get a low-pressure process of about 100Pa or more. Low-pressure process was carried out on the plasma confined, because mean free pass is very short. And, ion energy distribution (IED) is also controllable by low-presser process with VHF bias. The bimodal IED changes under low-pressure. The peak of high-energy side is reduced, and a charge exchange peak appears. It is considered that the charge exchange is important to anisotropic Si etching with VHF bias. Finally, an etch rate of more than 60 μm/min was realized. It was found that the Si etch rate depended on fluorine radical density and ion energy distribution, so, the high rate was obtained by creating a high fluorine radical density condition by using a high pressure condition of 100Pa using a VHF-CCP reactor with an ultra confined system and SF6 gas chemistry.
8:20 AM PS+MN-WeM-2 Very Uniform and High Rate TSV Etching Process in Advanced NLD Plasma
Yasuhiro Morikawa, Takahide Murayama, Koukou Suu (ULVAC, Inc., Japan)
The h igh-density of thru silicon via (TSV) is indispensable to the utilization and improvement in performance of 3D-LSI. Advanced high aspect ratio TSV etching technologies are required for high-density TSV formation. We have developed a new etching system for TSV application. This s ystem is a planer type magnetic neutral loop discharge (NLD) plasma, which is named as advanced NLD. For high rate silicone etching, it is very important to understand not only the high density of the plasma generation but also the high density of fluorine atoms . In this study, a novel RF antenna ‘ M ulti Stacked rf A ntenna’ has also been developed for the purpose of high rate etching. This antenna consists of multistage spiral turn rf antennas to reduce self- inductance (L), and is increased from turn of spiral to extend the inductive coupling discharge region. T he L feature of this antenna is 0. 95 uH and it is a low L antenna compared to the standard spiral antenna (1.7uH) . As a result of performing the electron density measurement of the NLD plasma using this MS antenna, it succeeded in the high-density plasma production of 1x1012 / cm3 by the process pressure of 7 Pa. Next, the Si etching process development was performed using the a dvanced NLD etcher. Si etching characteristics employing advanced NLD plasma were studied with respect to distance from an antenna. As a result, the etching rate improved 4 times more compared to the standard NLD. Finally, the diameter of 1 .5 um was attained by the anisotropic etching of 8. 5 um/min, and the aspect ratio is 5.3 using the a dvanced NLD etcher.
8:40 AM PS+MN-WeM-3 Deep Reactive Ion Etch Process Optimization for Control of Sidewall Profile and Morphology as a Function of Aspect Ratio
Randy J. Shul, Robert L. Jarecki, Todd M. Bauer (Sandia National Laboratories); Michael Wiwi (LMATA Government Services)

Deep reactive ion etching (DRIE) has become an enabling technology for the fabrication of many integrated microsystems, including accelerometers and gyroscopes, micro-fluidic devices, sensors, electrostatically actuated devices, and devices requiring back side optical access. The ability to etch deep Si structures with anisotropic sidewalls hundreds of microns deep has established a new set of devices in the MEMS area. Significant improvements in equipment and understanding of the process conditions have improved device yield and performance, and process reliability. Even with these improvements, several process issues are not well understood and often limit applications for the process. For example, sidewall morphology is often dominated by scalloping created by the iterative deposition-depassivation-etch cycle. Scalloping may make it difficult for deposition of materials on the sidewalls post DRIE or create non-optimal flow conditions for micro-fluidic devices. In addition, profile control of deep structures as a function of aspect ratio has not been optimized. For example, we have observed that creating positively tapered trench sidewalls often results in a trench bottom that exhibits a characteristic micromasked, grassy appearance. Conversely, eliminating the grass often results in a profile that undercuts the etch mask. Depending on the application, these phenomenon prevent the use of DRIE for device fabrication or cause the process to be optimized for specific structures thus preventing yield of other structures. In this presentation, we report on our efforts to vary DRIE process conditions to optimize sidewall profile and sidewall morphology as a function of aspect ratio. Structures considered in this study range from 10 microns to 700 microns in width, with etch depths to several hundred microns. We observe that passivation time, as well as ion energy, and ion flux in both the depassivation and etch cycles, have significant effect on the sidewall profile as a function of aspect ratio. We have also included morphing experiments in this study, where morphing is changing DRIE process parameters as a function of total process time. To optimize sidewall profile and morphology, the magnitude of the process changes during the morphing process is not necessarily linear with time. Results of these experiments will also be reported.

Sandia National Laboratories is a multi program laboratory operated by Sandia Corporation, a Lockheed Martin Company for the United States Department of Energy’s National Nuclear Security Administration under contract DE-AC04-94AL85000.

9:00 AM PS+MN-WeM-4 XeF2 Vapor Phase Silicon Etch used in the Fabrication of Movable SOI Structures
Jeffrey Stevens, Randy J. Shul (Sandia National Laboratories); Michael Wiwi, Christine Ford (LMATA Government Services); Thomas Plut, Todd M. Bauer (Sandia National Laboratories)

Vapor phase XeF2 has been used in the fabrication of various types of devices including MEMS, resonators, RF switches, and micro-fluidics, and for wafer level packaging. In this presentation we demonstrate the use of XeF2 Si etch in conjunction with deep reactive ion etch (DRIE) to release single crystal Si structures on Silicon On Insulator (SOI) wafers. XeF2 vapor phase etching is conducive to the release of movable SOI structures due to the isotropy of the etch, the high etch selectivity to silicon dioxide (SiO2) and fluorocarbon (FC) polymer etch masks, and the ability to undercut large structures at high rates. Also, since XeF2 etching is a vapor phase process, stiction problems often associated with wet chemical release processes are avoided. Monolithic single crystal Si features were fabricated by etching continuous trenches in the device layer of an SOI wafer using a DRIE process optimized to stop on the buried SiO2. The buried SiO2 was then etched to handle Si using an anisotropic plasma etch process. The sidewalls of the device Si features were then protected with a conformal passivation layer of either FC polymer or SiO2. FC polymer was deposited from C4F8 gas precursor in an inductively coupled plasma reactor, and SiO2 was deposited by plasma enhanced chemical vapor deposition (PECVD). A relatively high ion energy, directional reactive ion etch (RIE) plasma was used to remove the passivation film on surfaces normal to the direction of the ions while leaving the sidewall passivation intact. After the bottom of the trench was cleared to the underlying Si handle wafer, XeF2 was used to isotropically etch the handle Si, thus undercutting and releasing the features patterned in the device Si layer. The released device Si structures were not etched by the XeF2 due to protection from the top SiO2 mask, sidewall passivation, and the buried SiO2 layer. Optimization of the XeF2 process and the sidewall passivation layers will be discussed. The advantages of releasing SOI devices with XeF2 include avoiding stiction, maintaining the integrity of the buried SiO2, and simplifying the fabrication flow for thermally actuated devices. Sandia National Laboratories is a multi program laboratory operated by Sandia Corporation, a Lockheed Martin Company for the United States Department of Energy’s National Nuclear Security Administration under contract DE-AC04-94AL85000.

9:20 AM PS+MN-WeM-5 SF6/O2/HBr Plasma Processes for the Etching of High Aspect Ratio through Silicon Via
Sébastien Avertin (STMicroelectronics, France); Erwine Pargon, Thierry Chevolleau (Ltm - Umr 5129 Cnrs, France); Francois Leverd, Pascal Gouraud, Christophe Verove (STMicroelectronics, France); Olivier Joubert (Ltm - Umr 5129 Cnrs, France)
Today, the integration density and the chip dynamic power consumption are limiting and restricting phenomena. More than 50% of this consumption is due to long horizontal interconnects, and this rate is projected to increase. One solution to resolve these problems is 3D-Integration which provides smaller wire-length distribution by minimizing the connection length thanks to the fabrication of vertical vias through the silicon substrate or/and the chip. The ITRS roadmap requirement is to etch vias with 2-5 µm in diameter and high aspect ratio (>5). For deep silicon etching, the Bosch etch process which consists in alternating isotropic etching and deposition steps leads to the formation of the so-called scalloping phenomenon on the sidewalls (>100nm). In this paper, we propose to characterize and develop conventional plasma etching processes as an alternative to the Bosh process. The etching development is carried out in ICP reactor accepting 300mm wafers (DPSII from AMATTM) using SF6/O2/HBr plasma chemistries. The scientific objectives are to study the etching mechanism and passivation layer formation in order to get high etch rate (>3µm.min-1), straight profiles and a controlled undercut (<50nm). The etching profiles and etch rates have been analysed using Scanning Electron Microscopy while etch and passivation mechanisms have been studied by quasi-in-situ X-ray Photoelectron Spectroscopy (XPS) and plasma diagnostics (Mass Spectroscopy, ion flux probe..). Preliminary results indicate that the etch mechanisms are strongly driven by the ratio of neutral over ion fluxes and that the etch process is very sensitive to microscopic effects such as the local loading of fluorine and oxygen radicals which is directly correlated to the local pattern density. Through a better understanding of the etch mechanisms, high aspect ratio silicon via with anisotropic profiles and minimized undercut have been obtained.
10:00 AM BREAK - Complimentary Coffee in Exhibit Hall
10:40 AM PS+MN-WeM-9 Key Challenges in Extremely High-Aspect- Ratio Dielectrics Etching at 3x nm DRAM and Beyond
Sungkwon Lee, Jun-Hyeub Sun, Sang-Oh Lee, Jong-Sik Bang, Si-Young Lee, Chang-Moon Lim, Su-Young Kim, Dong-Guy Lim, Sung-Ki Park, Young-Gyun Jung (HYNIX Semiconductor Inc., Republic of Korea)
One of key issues in fabricating the dynamic random access memories (DRAM) is to control the vertical profile effectively during the etching of a SiO2 high aspect ratio contact holes (HARC). In order to ensure acceptable Cs (>25fF/Cell) for DRAM at half pitch (HP) 3x nm and beyond generation, it is required of fabricating cell capacitors having very highly aspect ratio above 50:1. Thus, the HARC etching technology to get smaller bowing width as well as larger opening area becomes the most difficult challenges among numerous DRAM fabrication steps. This is because of trade-off between both bowing and opening requirement during HARC etching. Although the mechanism of bowing and not-opening has reported in several studies at above 70nm technology nodes, still has not yet been reported at hp 3x nm and beyond. In this presentation, especially, we will focused on the HARC etching issues at Nitride Fence supported Capacitor (NFC) scheme which is used to prevent leaning. Capping is arose by several factors, which reduce the etch rates and cause the contact opening failure, then eventually affects on the electrical characteristics. The types of capping studied in this work can be divided into three categories as the etching proceeded, such as polymer pinch-off, excess polymer capping originating from polymer rich chemistry at top region, and non-steady polymer deposition and removal at etch front. In this study, we investigated that capping issues become more serious when 2MHz range power is added to increase contact opening margin. To avoid these types of different failures aforementioned, it is necessary to understand the plasma etching behavior at hp 3x nm and beyond compared to previous technology nodes. In addition, beyond typical bowing position, an additional bowing position at NFC is also key concern issues within oxide layer between hard mask (HM) and Nitride from the wafer top surface. This is caused by the ions scattered from the mask side-wall slope on the contact-hole. It can be reduced effectively by adjusting HM material, thickness, and etching conditions. Especially, HARC etching parameters also play an important role to suppress the bowing and capping. We will report here how contact hole’s opening and bowing are enhanced, and how they can be controlled by adjusting etching conditions also. It is suggested that optimizing the etching condition with a suitable concept in this work would be the most effective solution during the HARC etching process. Consequently, Key approaches on HARC etch processes for fabricating of a contact hole in SiO2 with aspect ratios of 50:1 and beyond were evaluated in this work in detail.
11:00 AM PS+MN-WeM-10 Microstructures Etching on Silicon with the STiGer Process
Thomas Tillocher (GREMI, France); Julien Ladroue (GREMI - STMicroelectronics, France); Franck Moro, Guillaume Gommé, Philippe Lefaucheux (GREMI, France); Mohamed Boufnichel (STMicroelectronics, France); Pierre Ranson, Rémi Dussart (GREMI, France)

The STiGer cryoetching process can be alternatively used to the Bosch process or the cryogenic process to etch high aspect ratio structures. It has been developed thanks to our knowledge of the passivation mechanisms in cryoetching. In the standard cryogenic process, patterned Si substrates cooled down to very low temperatures are exposed to continuous SF6/O2 plasmas. A SiOxFy-type passivation layer is formed on the sidewalls and prevents etching. This film has the property to desorb under ion bombardment or when the substrate is heated. We also showed that SiF4/O2 plasmas can be used to create or reinforce a passivation layer in cryogenic etching.

The STiGer process consists of cycling passivation steps (SiF4/O2 plasmas) and etching steps to get vertical structures. The etching steps can be either isotropic (SF6 plasmas) or anisotropic (SF6/O2 plasmas). Like the cryogenic process, it is required to cool the Si substrate with liquid nitrogen.

The STiGer process combines advantages of both Bosch process and cryogenic process. Due to the cyclic passivation steps, the SiOxFy film is stronger than in “standard” cryoetching. In addition, the passivation layer desorbs when the substrate is heated back to room temperature. Thus, unlike the Bosch process, there is no need to clean the microstructures and the chamber walls after each process run. Moreover, the robustness is enhanced in comparison with “standard” cryoetching : the profiles are less sensitive to temperature variations.

But, like the standard cryogenic process, a cooling is required and like in Bosch etching, a scalloping is present on the sidewalls. However, it is possible to minimize this effect by tuning the etching and the deposition steps.

We will present our most recent performances with the STiGer process. Our objectives are to etch sub-micron trenches and holes that will be further used for the realization of integrated capacitors and Through Silicon Vias (TSV). But obviously, the STiGer process can be utilized for silicon micromachining in general.

Finally, we will see how such a process can amplify Columnar MicroStructures (CMS).

Time Period WeM Sessions | Abstract Timeline | Topic PS Sessions | Time Periods | Topics | AVS2010 Schedule