With the downscaling of CMOS devices in semiconductor industry, very thin layers (<1.5nm) are now introduced in transistor gate stacks. Integrating such thin layers presents tremendous challenges, particularly for the etch processes which have to be stopped selectively without inducing damage to the thin materials below. For instance, bulk silicon may be oxidized during the gate over-etch step through the thin gate oxide, which leads to silicon recess during the subsequent wet cleanings. In this contribution, we will precise the mechanisms of silicon oxidation through the thin gate oxide, and we will propose solutions to minimize this phenomenon by pulsing the plasma.

The experiments are performed on a state of the art 300mm AdvantEdge^TM etch reactor equipped with the Pulsync^TM system which provides full plasma pulsing capabilities at frequencies between 100 Hz and 20 kHz, with duty cycles between 10 and 90 %. In-situ spectroscopic ellipsometry is used to determine etch rates on thick silicon oxide and polysilicon layers, and to investigate plasma induced oxidation through a 2.5nm thin silicon oxide coated on bulk silicon. An angle resolved XPS system connected to the reactor allows quasi in-situ surface characterizations.

We show that an infinite selectivity of polysilicon over SiO₂ is obtained using an HBr/O₂/Ar gate over etch process on thick layers. However, when a thin layer of silicon oxide is exposed to the same process, the thin oxide layer thickness increases with the plasma exposure time. This thickness increase is related to plasma induced oxidation through the thin gate oxide. XPS analysis show that a Si-Br_x interface layer builds up between SiO₂ and Si, and that some bromine is incorporated in the oxide. This suggests that bromine implantation through the SiO₂ layer may generate a path in the oxide layer facilitating the oxygen and water diffusion (from the plasma or from the atmosphere) down to the SiO₂/Si interface

We show that plasma induced oxidation can be minimized by using synchronous pulsed plasmas. This way, we move from a highly dissociated plasma to a highly recombined plasma. As a consequence, radicals are larger and less prone to diffuse, and ions are molecular rather than atomic, which decreases the net energy of their components. Hence, bromine incorporation is highly limited and no Si-Br_x interface layer is created, which minimizes silicon oxidation through the thin gate oxide.

These experiments clarify the mechanisms of plasma induced oxidation through the thin gate oxide, and show the promises of synchronous pulsed plasmas to reduce silicon recess.

To continue scaling CMOS devices at the traditional pace following Moore ’s law, Short Channel Effects (SCE) are the major issues limiting the use of planar device geometries for future technology nodes. Alternative device integration schemes are currently being tested to test the impact on SCE and extend technology nodes even further. The device candidates that are currently being tested include planar devices, FinFETs, Trigates and Nanowires (gate all around device). The gate formation on these advanced, multi-gated devices imposes completely new challenges on the plasma etch conditions, which translates to the demand to control the plasma process in a second (and a third) dimension. E-beam lithography has been proven to be a very valuable tool to explore plasma processing at device sizes unattainable by state-of the art optical lithography. We have demonstrated the fabrication of gates above a Fin of varying dimensions of gate and fin for SRAM cells down to 0.025um². Significant challenges for this integration lie in the gate as well as the spacer formation, while maintaining the Si fin that has no hardmask to prevent plasma damage. While maintaining a vertical gate profile, no Silicon loss was observed on the Si Fin. A more significant challenge is the spacer formation, where Nitride needs to be removed from the fin sidewall, while maintaining it on the gate sidewall to prevent device shorts. An even higher degree of process control is needed in the fabrication of nanowire or gate all around devices. Maintaining a vertical gate profile while not damaging or destroying nanowires of diameters less than 5nm is critical. A gate recess process was employed to release the nanowire structures. A highly selective spacer rie process was developed to yield nanowires down to 3nm in diameter.

New materials such as High-K/Metal Gate and three-dimensional structures such as Tri-Gate have been introduced at the 22nm node and beyond. In addition, high selectivity and reduced Plasma Induced Damage (ex. Charge up damage and Si crystal damage, etc.) are required of the etching process. Especially, Fin Spacer of Tri-Gate is required high selectivity to thin oxide. RLSA (Radial Line Slot Antenna) microwave plasma has several features that overcome these new challenges. The characteristics of RLSA plasmas include high density, low electron temperatures and low plasma potential. In addition, Radical/ion ratio is higher than conventional plasma source. These characteristics enable highly selective etching with decreased Plasma Induced Damage on the wafer surface. A high SiN/SiO selectivity process has been achieved due to the features of RLSA plasma and low bias (low Vpp) conditions.

As the Critical Dimension (CD) of gate transistors scales down to the nanometer range, line width roughness (LWR) becomes a serious issue, which directly impacts the electrical performance of CMOS devices. It has previously been shown that the photoresist (PR) sidewall roughness present after lithography (6nm, 3σ) is transferred during the subsequent plasma etching processes into the gate, resulting in a final LWR far above the ITRS requirements for the 32nm technological node (1.7nm, 3σ). The key to decrease the final gate LWR is to minimize the photoresist LWR before the plasma etching steps involved in the gate patterning process. The best and simplest way is to expose the photoresist patterns to plasma treatments prior to gate patterning. Indeed, it was observed that Vacuum Ultra Violet (VUV) light emitted by plasmas plays a key role in the photoresist LWR decrease. In the present study, we have used CD-SEM and CD-AFM techniques to investigate the impact of plasma treatment on the photoresist LWR and profiles. Several plasmas (HBr, Ar, He, H₂) emitting strongly in the VUV region (100-200nm) have been investigated. LiF windows placed between the plasma and the photoresist patterns have been used to evaluate the role of the plasma VUV light only on the LWR evolution. The role of the substrate temperature has also been studied. Many characterization techniques have been used to characterize the physico-chemical modifications of photoresist films exposed to the same plasma treatments (Multiple Internal Reflection infrared spectroscopy (MIR), Raman, gas chromatography (GC)).

The results obtained indicate that all plasma treatments lead to a LWR decrease. We have observed that for all plasma investigated, VUV light only seems to induce a slight reflow of the resist which is probably correlated with the LWR decrease. On the other hand, in HBr and Ar plasmas, resist patterns remain square indicating that no reflow occurs. Heating resist patterns up to 200°C without plasma exposure also leads to a LWR decrease, resist reflow being only observed above 200°C . All treatments generate the cleavage of the side groups (lactone group for plasma treatment and protecting group for annealing treatment) and the decrease of the glass transition temperature which is potentially correlated to the LWR decrease. GC analysis also reveals that under Ar and HBr plasma exposure, cleaved side groups can be trapped in the resist polymer matrix because of the presence of a denser surface layer. This dense layer could prevent the resist reflow leading in final to the square profiles observed in HBr plasmas.