The choice of copper/Low-k interconnects architecture is one of the keys for integrated circuits performances, process manufacturability and scalability. Today, the implementation of porous low-k material becomes mandatory in order to minimize the signal propagation delay in the interconnections. In this context, the traditional plasma processes issues (the plasma-induced damages, dimension and profile control, selectivity) and new emerging challenges (sidewalls surface roughness, dielectric wiggling) become the critical points to control the reliability and defectivity.

Based on plasma-surface interaction understanding, the main issues and also the potential solutions will be illustrated through different process architecture using metallic or organic hard masks strategies.

As scaling of microelectronic devices approaches sub 30nm nodes, many material and module process challenges in BEOL plasma patterning have been reported. One of the methods that has gained traction over recent years for enabling sub 20nm feature patterning is the Trench First metal Hard Mask (TFmHM) scheme. While this scheme solves or mitigates many challenges that are inherent with Via First Trench Last (VFTL) Scheme, it introduced other dielectric RIE process and hardware challenges. One of the root causes of the former is the fact that all patterns and materials are exposed to plasma at the same time. As such, the simultaneous control of via, trench and chamfer profiles (i.e. Critical Dimensions, depth, taper profile, etc), the need to control selectivity between multiple patterning layer (TiN, TEOS, ULK, Barrier cap, etc), and ULK damage control has become more pertinent in the dielectric etch. As the direct result of such tight process guidelines, the hardware challenges arise and new dimensions in process controls are needed. The prolonged exposure of the TiN to the plasma created the need for more robust production worthy hardware. The required selectivity of the materials necessitate temperature controllable chucks. The more complex patterning techniques require ULK preservation and other uniformity controls. In this paper, the RIE efforts on process controls of the profiles, material selectivity, associated hardware challenges and possible future roadmaps under TFmHM scheme will be discussed.

This work was performed by the Research team at TEL Technology Center America in joint development with IBM Research Alliance Teams in Albany, NY.

As feature critical dimension (CD) shrinks towards and beyond the 22nm node, limitations of traditional patterning processes become critical. Conventional 193nm immersion lithography is not able to resolve trenches below 40nm half pitch with a single exposure. Patterning vias at appropriate CD and spacing is equally challenging. Extreme ultraviolet (EUV) lithography offers appropriate k1 reduction to solve these problems, but the equipment and metrology infrastructure is not in place to support 15nm node development on a large scale. Thus, much of the industry's attention is being paid to double patterning techniques based on existing 193nm imaging capability. In this paper, we will discuss various double patterning schemes and the associated technical challenges for plasma etching - both for generating patterns with sub-40nm half pitch and for utilizing the resultant masking stacks for BEOL etching. In particular, we will review the issues associated with applying "double-exposure double-etch" sequences, "double-exposure single-etch" approaches, and sidewall image transfer to formation of dual-damascene structures in advanced ultra low-k dielectrics.

This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities.

1. Lee et al., Thin Solid Films, 517, (2009)
2. Zhou et al. AVS 2009. http://www.avsusergroups.org/pag_pdfs/2009_6zhou.pdf .

Higher porosity and new film chemistry are required to drive down k value of porous ultra low k (ULK) dielectrics integrated in advanced BEOL stacks. The challenge of integrating ULK dielectrics is compounded by shrinking dimensions. Taking a tri-layer resist via-first-trench-last integration scheme as an example, as the technology nodes progress, lower k value dielectrics are more prone to ashing damage. The resulting damaged layer accounts for a larger percentage of remaining film, resulting in higher integrated k value. Therefore, ashing improvement achieved for earlier nodes is not sufficient for the 22nm node. A particular ULK integration challenge is via to line spacing. The tight pitches at 22nm leave little tolerance for enlargement of the via size and shape. Previously acceptable levels of profile bowing can now directly lead to shorting. In this work, the challenges of ashing damage and via profile bowing are examined with a via first trench last integration scheme. It is identified that ashing is responsible for the majority of via profile bowing, and the key to reducing via bowing and ashing damage is to improve the ashing selectivity of organic mask to dielectrics. Different approaches are taken to improve ashing selectivity, including the traditional ashing chemistry/plasma optimization and a new pre-ash dielectric passivation scheme. These optimizations have significantly improved both physical and electrical performance.

The dual frequency capacitively coupled plasma (CCP) with negative DC bias superimposed to the upper electrode has been proposed to realize high performance etching technologies. Denpoh et al. have discussed a mechanism under the DC bias superimposition that secondary electrons generated at the upper electrode transport through a bulk Ar plasma to the counter electrode. Kawamura et al. have also discussed about effects of the secondary electrons and a characteristic of the superimposed DC/RF sheath. Since the fluorocarbon (CF) etching plasma with the DC bias has not ever analyzed, we have measured various parameters and discuss the effect of the DC bias on the selective etching of SiOCH over SiC.

We used a CCP reactor for 300 mm wafer. VHF (60 MHz) power and DC bias were simultaneously applied to the upper electrode. RF (13.56 MHz) power was applied to the lower electrode where the samples were placed for etching experiments. A mixture gas of Ar, N₂ and C₄F₈ introduced with flow rates of 800, 100, and 10 sccm, respectively. Pressure was kept at 5.3 Pa.

Bulk plasma parameters such as electron density and CFx densities were measured when the DC bias changed. The electron density was 1.3×10¹¹ cm^-3 without the DC bias. In contrast, with the bias of -1200V, that gained up to 2.1×10¹¹ cm^-3. This increase can be interpreted that positive ions accelerated by the DC bias bombarded the upper electrode with higher energy and then generated and supply more secondary electrons to the bulk plasma.

Notably, CF₂ radical density was decreased from 2.5 to 1.5×10¹³ cm^-3 with the DC bias. It is well known that the bulk density depends on the surface loss probability, α, of the CF₂ radical. The α gained by dangling bonds creation by the ion bombardments. As the result, we believed that more fluorine-rich compounds in bulk plasma were lost by the adsorption and reaction on the reactive surfaces. In fact, with the DC bias of -1200V, SiOCH/SiC selectivity was improved significantly to 68 from 5.5without the DC biasing. This improvement was mainly brought by the etch rate decreasing SiC from 18.5 to 1.3 nm/min while the etch rate of the SiOCH film was maintained almost constant.

Surface analysis results showed that CF polymerized layer was not grew thicker on the SiOCH by such chemical reactions as C + O → CO, C + N + H → HCN. However, in the SiC case, a polymerized layer was relatively thicker because removal reactions were suppressed by lack of F-rich compound. Consequently, the highly selective etching for SiOCH/SiC films was achieved by differentiating the polymerized layer formation.