Papers

AVS2004 Session PS+MS-TuA: 45nm Node with Panel Discussion

Tuesday, November 16, 2004 1:20 PM in Room 213A

Tuesday Afternoon

Start	Invited?	Item
1:20 PM		PS+MS-TuA-1 Preliminary Investigations for Ultimate Gate Patterning E. Pargon (LTM-CNRS, France); J. Foucher (CEA-LETI, France); J. Thiault, O. Joubert (LTM-CNRS, France) The fabrication of a sub-20nm transistor gate requires a very accurate control and understanding of all the plasma steps (resist trimming, BARC, hard mask open and gate etch) involved in the gate stack processes. Then, it is important to study the parameters that can generate a deviation of the final gate dimension for each of these plasma steps. The two aspects that we have studied are the etching behaviour of the photoresist mask exposed to the plasma, and the chemical nature of the layers that deposit on the reactor walls and feature sidewalls during the process. We have developed an experimental procedure using XPS analyses to characterize the chemical modifications occurring on the tops and sidewalls of the photoresist mask as well as the chemical nature of the coatings formed on the chamber walls. These analyses can be correlated with the process performances (in terms of etch profile and critical dimension control (CD control). SEM observations and CD AFM 3D have been used to get the process performance. In all the plasma conditions investigated, the BARC and hard mask opening steps both lead to a CD deviation of 5 to 15 nm attributed to the modifications of the photoresist mask during plasma exposure. XPS analyses and 3D AFM measurements show that the passivation layers formed on the pattern sidewalls during the gate etch step itself are strongly influenced by the pattern density and etch chemistry. Finally, we show that the only way to control gate etch processes in the sub 20 nm range is to minimize strongly the formation of the passivation layers on the gate sidewalls.
1:40 PM		PS+MS-TuA-2 EUV Light Source Development and Debris Mitigation For 45nm Node Lithography and Beyond B.E. Jurczyk, M.A. Jaworski, M.J. Neumann, M.J. Williams, D.N. Ruzic (University of Illinois at Urbana-Champaign) Discharge-produced plasma (DPP) light sources are leading candidates for generating 13.5-nm wavelengths needed for next-generation optical lithography. Traditional DPP sources have used xenon radiators due to its cleanliness; however, high output requirements (>115W at first focus) are driving developers towards higher conversion efficiency fuels such as tin. As a result, condensable tin vapor and electrode debris reaching and damaging the first collector optic is a serious concern for device lifetime and cost of ownership. A secondary-plasma debris mitigation technique was successfully demonstrated for noble gas light sources at the Illinois Debris-mitigation EUV Applications Laboratory (IDEAL). The IDEAL facility utilizes a dense plasma focus discharge source operating at nominal conditions of 15 J/pulse, 50 Hz rep rate, and 3 kV. Electrode sputtered debris is re-ionized in a secondary plasma region and removed with a biased foil trap prior to the collection optics. For a low density plasma (10⁹ cm^-3) condition, a debris removal fraction of 61% ± 3% was observed. The experimental chamber has been modified to operate with tin delivery into the pinch region. Results from electrode redesign, tin injection, EUV light output and condensable tin vapor mitigation will be presented. High density results from an improved internal helical-resonator shielded inductive coil configuration give greater protection efficiency. Fast ions contributing to optic erosion have been observed. Results from a gridded energy analyzer shows two peaked ion distributions at 2.8 keV and 5.8 keV. Elevated plasma potential and sheathing effects have shown an increase in ion energy at the boundaries. An improved ESA/TOF system provides < 5 eV spectral energy resolution and information on charge/mass ratio. Preliminary results from the new Surface Cleaning of Optics by Plasma Exposure (SCOPE) facility are presented for advanced fuel interactions on optical components.
2:00 PM		PS+MS-TuA-3 Fundamental Studies on Low-k Processing T. Tatsumi (Sony Corporation, Japan) The need for reliable low-k/Cu interconnect technologies is increasing, and many kinds of low-k materials have been proposed. We need a process design for etching that will correspond to a change in the film densities and compositions of low-k materials for 90 and 65-nm node devices. Using many different in-situ plasma-measuring tools, such as IRLAS, OES, surface wave probes, and QMS, we counted the absolute number of incident species (CF_x, O, N, H, F, radicals and ions) that were dissociated and/or ionized in fluorocarbon plasmas. Next, we evaluated the surfaces of the various SiOCH films (k = 2.9-2.2) that had different film compositions and densities, and that had been exposed to various fluorocarbon plasmas. The etch rates, selectivity, and thicknesses of the surface polymers were analyzed. We found that the etch rates of the SiOCH films depended on both the "total number of F atoms in all of the incident CF_x reactive species", and "the surface reaction probability, which depends on ion energy". Lower oxygen concentrations in SiOCH film induce a narrower process window because the fluorocarbon polymer became thicker, even during lower incident CF_x flux conditions.¹ As a result, the etch rate became very sensitive to changes in the incident CF_x fluxes, resulting a narrow process window for etching SiOCH and porous SiOCH materials. To ensure reliable interconnects for 45 nm and beyond, we require new technologies to realize both "quantitative control" and "instant stabilization" of the plasma parameters. Furthermore, we also need to develop a model to control the atomic layer modification (etching and/or degradation) of the actual etched surface for various materials. Cooperation between etching and other unit process engineers must be promoted in order to create a more reliable process module. ¹ T.Tatsumi et al, Proceedings of the 2003 IITC (2003) 239.
2:40 PM		PS+MS-TuA-5 Plasma Etch Challenges for 45 nm Node and Beyond R. Wise (IBM) Many novel technologies are candidates for introduction at the 45 nm technology node. Metal gate electrodes, high-k gate dielectric materials, hybrid oriented transistors (HOT), FINFET transistors, new silicide materials, multiple stressed liners, fully-silicided gates, and porous low-k BEOL materials are all currently under evaluation for introduction at the 45 nm node. The anticipated impact of each of these technology components on requirements of dry etch process and tooling is discussed in detail. Lithographic limitations will continue to require dry etch processes (e.g. gate, contact) to provide additional CD reduction to meet designed groundrules. These processes will include extension of well-known resist trim techniques as well as other techniques, such as providing a controllable taper through a sacrificial masking material. Available resist material will be reduced both by limitations of the lithographic process window (N.A , DOF, resolution ) as well as implementation of multiple exposure techniques. These reductions in the available mask thickness required to preserve lithography process window have driven the need for highly selective etch processes, generally at the expense of uniformity (especially on 300 mm wafer sizes), defectivity, and profile of the transferred pattern. Later generation lithographic materials are expected to continue to exhibit increased sensitivity to line edge roughness. Process and tooling needs required to address these lithographic challenges are discussed.
3:20 PM		PS+MS-TuA-7 Invited Panel - "Challenges for 45 nm Node" C. Gabriel (AMD (damage)); M. Hussein (Intel (scaling)); C.-J. Kang (Samsung (dielectric etch)); S. Wege (Infineon (silicon etch)) Panelists will present 5-minute perspectives.
3:40 PM		PS+MS-TuA-8 Discussion - "Challenges for 45 nm Node" Panelists and Attendees