AVS2004 Session CT-MoA: Material Solutions for Chip Cooling

Monday, November 15, 2004 2:00 PM in Room 303B

Monday Afternoon

Start	Invited?	Item
2:00 PM	Invited	CT-MoA-1 Natural Power Scaling Trends in Microprocessors and Other Complex Logic E.A. Burton (Intel Corporation) The last decade has seen a continual growth in the size and complexity of cooling solutions for mainstream personal computers. Natural CMOS scaling trends, and the competitive nature of the electronics industry, have been the twin drivers of this aggressive cooling technology trend. Every 18 months a new silicon processing node is developed, which doubles the number of transistors that can be packed into a given sized die. Although these new transistors are half the area of the ones they replace, they are faster and have a higher capacitance density. The end result is an exponential power scaling trend with a doubling of power every few years. This trend is clearly evident in Central Processing Units (CPUs), where the power has increased roughly 10x in a decade. The same exponential power-growth trend is also showing up in graphics processor chips (GPUs), where recent high-end products sport dual-slot cooling solutions with heatpipes, fans, and ducted airflow.¹ Although at first glance the roughly 10x per decade power-scaling trend would seem to signal impending disaster, a reduction in the performance vs. time ramp can immediately stop the power ramp. Market forces will be the deciding factor in setting the future power vs. time ramp. Integrated circuit manufacturers will have to plan their future performance ramp carefully to ensure the ramp is economically sustainable. Since the future performance trend will be limited largely by the capability and affordability of the cooling technology, integrated circuit cooling has taken on a profoundly strategic importance. Since exponentially shrinking the flagship die-area is an obvious means of stopping the future power ramp, even a constant power vs. time is likely to present a serious cooling challenge. A fixed power limit combined with steadily shrinking die sizes results in steadily increasing power density. Such a trend presents an obvious materials challenge, or perhaps a strategic opportunity - depending on one's point of view. This paper explores the underlying silicon scaling trends driving the increasingly important field of integrated circuit cooling. Since increasingly difficult and costly cooling will change the underlying scaling trends, altered scaling scenarios are also studied. These altered scaling studies are not intended to be an exhaustive optimization, but rather to explore sensitivity or likely range of difficulty a materials scientist might expect to face in the future. It is hoped this will set the stage for following papers, which delve deeper into actual cooling materials science. ¹http://www6.tomshardware.com/graphic/20040414/geforce_6800-05.html
2:40 PM	Invited	CT-MoA-3 Challenges and Opportunities for Cooling Advanced Semiconductor Devices D. Seeger (IBM T.J. Watson Research Center) As CMOS technology continues to evolve, direct scaling has become increasingly difficult. As a result, the rules of scaling have been 'fudged' in order to stay on the historical Moore's law curve. In particular, power has not decreased at a rate consistent with Moore's Law though chip area has scaled. As a result, chip power densities are increasing rapidly. Chip power densities for CMOS technologies today rival that of bipolar devices of the last decade. At that time, the industry was focused on developing advanced chip cooling technologies to deal with the high powered bipolar devices of the time. However much lower power CMOS device technology came along to ‘save the day’ and allowed most of these advanced chip cooling technologies to be shelved. Today we face a similar situation for chip power densities. However there is no comparable low power technology on the horizon and as a result, the power density problem must be solved. In thinking about this problem from the chip to the package, the first surface the chip faces is typically a heat spreader made of copper or other high thermal conductivity material. In order to insure good thermal contact, a thermal interface material (TIM) is sandwiched between the chip and the heat spreader. These materials are two orders of magnitude better in thermal conductivity than air, hence the reason for their existence. However, they are typically two orders of magnitude LOWER in thermal conductivity than the other materials in the chip/package stack. Given that this is the most important interface in the stack, a lot of focus has been placed on improving the thermal conductivity of TIMs. Since the heat spreader has a significantly different thermal coefficient of expansion than the chip, compliant mechanical considerations are also important. Then, intimate thermal contact to an efficient heat sink must be accomplished. Once at the heat sink level, the heat must be expelled to the air and then carried out through the computer box, racks in the case of servers. Finally, this heat needs to be removed from the data center. All of the above components must be optimized as a system since any single point in the thermal path can choke off the flow of heat and dramatically decrease the efficiency of heat removal from the system. This talk will be an overview of these issues and the technologies being developed to overcome them
3:20 PM	Invited	CT-MoA-5 Overview of the Heat Removal by Thermo Integrated Circuits (HERETIC) Program at the Defense Advanced Research Projects Agency (DARPA) D.J. Radack (Defense Advanced Research Projects Agency (DARPA)) The objective of the HERETIC program is to develop solid-state and fluidic heat removal devices that are integrable with dense, high-performance electronics and photonics. These devices are envisioned to short-circuit the thermal resistance between heat sources and thermal sinks; they should also lead to a reduction in overall system volume and weight. It is expected that devices will be designed for high efficiency operation (in terms of work done to remove a unit of heat from a hot junction). Traditional thermal management in many electronic and optoelectronic systems is generally relegated to the end of the process sequence in the packaging of the systems. For non-critical applications, where the systems are used in relatively benign environments, this approach is cost-effective and has worked well. This ad hoc method of thermal management is inadequate and the need for new or novel approaches becomes clear for certain situations. These situations may be: where the system package must be small and compact; where the density of high-performance, high-power chips on a board is high; or where the environment is thermally harsh. In conventional thermal management, heat removal or cooling is typically addressed hierarchically. The first level of the hierarchy is at the system level, the second is at the board level, and the third is at the chip-package level. As a common example, consider the following case: at the system (box) level, global air circulation may be effected by a fan that blows over boards that comprise the system; at the board level, the chips may be mounted on a board that allows the circulation of a coolant through it; and, at the chip-package level, the package (containing a telecommunications laser chip or a special processor chip, for example) could be cooled directly by a thermoelectric cooler. The focus of this program is at chip and board levels.
4:00 PM	Invited	CT-MoA-7 Liquid Cooling Technologies for Microprocessors T.W. Kenny, K.E. Goodson, J.S. Santiago (Stanford University); M. Munch, G. Upadhya, D. Werner, M. McMaster (Cooligy, Inc.) Recent trends in processor power for the next generation devices point clearly to significant increase in processor heat dissipation over the coming years. In the desktop system design space, the tendency has been to minimize system enclosure size while maximizing performance, which in turn leads to high power densities in future generation systems. The current thermal solutions used today consist of advanced heat sink designs and heat pipe designs with forced air cooling to cool high power processors. However, these techniques are already reaching their limits to handle high heat flux, and there is a strong need for development of more efficient cooling systems which are scalable to handle the high heat flux generated by the future products. To this end, a new closed loop liquid cooling system has been developed to handle heat fluxes greater than 500 W/sq cm. The cooling system comprises a micro channel heat exchanger for high heat flux removal capability, an electro-kinetic pump for delivering fluid with required flow rate and pressure, coupled with a counterflow heat rejecter to dissipate heat to the ambient. This talk will describe the components of this technology and discuss the process taken to transition from DARPA-Funded academic research to venture-funded startup to successful company.
4:40 PM	Invited	CT-MoA-9 Microfluidic Technologies for Integrated Thermal Management A. Glezer (Georgia Institute of Technology) The development and demonstration of microfluidic-based, thermal management technologies for a diverse range of heat loads [O(10)- O(1000) W] are described. These technologies address both local and global stages of heat transport between integrated circuits and the environment into which the heat is ultimately rejected. The fluidic-based cooling approaches range from phase-change heat transport based on vibration-induced droplet atomization (VIDA) and vibration induced bubble ejection (VIBE), to controllable heat convection using micromachined synthetic air jet arrays. Examples of the implementations of these technologies include the integration of synthetic jet actuators with heat sink configurations to form an "active" heat sink, and with electronic substrates (e.g., printed wiring boards) to form an active cooling substrate (ACS), as well as the realization of compact, VIDA- and VIBE-based, phase-change heat transfer cells.