AVS1999 Session EM-WeP: Poster Session

Wednesday, October 27, 1999 5:30 PM in Room 4C
Wednesday Afternoon

Time Period WeP Sessions | Topic EM Sessions | Time Periods | Topics | AVS1999 Schedule

EM-WeP-1 Comparison of Plasma Chemistries for Dry Etching of Ta2O5
K.P. Lee, K.B. Jung, R.K. Singh, S.J. Pearton (University of Florida); C.C. Hobbs, P. Tobin (Motorola)
Inductively Coupled Plasma etching of Ta2O5 was performed in a variety of different chemistries, including SF6 with additions of O2, Ar, CH4 or H2 ; Cl2/Ar ; N2/Ar and CH4/H2/Ar. Etch rates up to ~1200 Å ú min-1 were achieved with either SF6 or Cl2 based chemistries. Under these conditions the etch rates for Si were approximately 4-7 times faster, although equi-rate etching was achieved at low source powers and low halogen gas percentages in the plasma chemistry. The etched Ta2O5 surfaces were smooth (RMS roughness ≤ 0.5 nm) over a broad range of conditions of source power, chuck power and process pressure. The etch rates with N2/Ar and CH4/H2/Ar were an order of magnitude lower than with SF6 or Cl2. There was no effect of post deposition annealing on the Ta2O5 etch rates, at least up to 800°C.
EM-WeP-2 Study of the Impact of Time-Delay Effect on the Critical Dimension of Tugnsten Silicide/Polysilicon Gate After Reactive Ion Etching
S.P. Lin, C.H. Ou, S. Lee, Y.C. Tien, C.F. Hsu (Winbond Electronics Corporation, Taiwan)
In the fabrication of submicron devices with high-density integration, the control of critical dimension (CD) of tungsten silicide/polysilicon gate becomes extremely crucial in device performance. To ensure a reliable gate patterning process, etching recipe with a very high selectivity is used to control the gate profile to be notching-free and vertical as well as keeping the gate oxide loss minimized. Besides the use of oxygen and chlorine-based chemistry in gate stack etching, HBr is also used to improve the selectivity of polysilicon to gate oxide. As a consequence of high selectivity, polymer residues become a major factor in CD control. It is believed that the presence of HBr in the plasma is responsible for polymer formation. HBr and its polymer residues may induce surface reactions to form thin oxide layers. Such a phenomenon has been observed if the wafers are not treated with HF vapor (for the removal of polymer residue) immediately after reactive ion etching (RIE) of the gate. The magnitude of the oxide film growth is proportional to the time delayed between RIE and HF vapor treatment. The sidewall thickness of the gate is also affected by the time-delay effect. The growth of oxide film on sidewalls can eventually affect the gate CD and thus the device performance. A simple reaction model for the growth of oxide film is proposed to explain the correlation between delayed time, CD bias, and product yield.
EM-WeP-3 Effects of Deposition Temperature of Co Thin Films on (100)Si
H.Y. Huang, L.-J. Chen (National Tsing Hua University, Taiwan, R.O.C.); W.F. Wu, R.P. Yang (National Nano Device Laboratories, Taiwan, R.O.C.); L.Y. Chen (United Microelectronic Corporation, Taiwan, R.O.C.)
Low resistivity silicide films have received a great deal of attentions because of their applications in ULSI in recent years. Low resistivty silicides have been widely used in source/drain as contacts. They reduce both the parasitic source/drain resistance and the contact resistance. Among all the silicides, NiSi, TiSi2, and CoSi2 are of the lowest resistivity. TiSi2 is currently the most common silicide used as contact metal in IC industry. However, as devices are scaled down to deep submicron dimensions, it is difficult to transform TiSi2 from high resistivity C49 phase to low resistivity C54 phase in small dimension features owing to the lack of nucleation sites. CoSi2 is also of low resistivity and has been a promising candidate to substitute TiSi2 for various processing advantages. In addition, its good lattice match with Si makes it possible to grow epitaxial silicide layer on Si. High temperature sputtering deposition (HTSD) was previously found to facilitate the phase transition from C49 to C54-TiSi2. This method also reported as a new salicide technology for deep submicron devices to reduce the complicated process steps including TiN capping layers and preamorphization of substrate. In the present study, the Co films were deposited at different temperatures from room temperature to 550° C on (001) Si using UHV sputtering cluster tools. One- and two-step annealings were performed. TEM, XRD and AES were used to examine the samples. HTSD was found to improve both the thermal stability of CoSi2 and CoSi2/Si interface smoothness.
EM-WeP-4 Growth of Ultra Thin Oxides of Silicon by Wet Oxidation Technique: Effect of Water Vapor Pressure
B. Viswanath Krishna, K.N. Bhat (Indian Institute of Technology, India)
The rapid scaling down of silicon device dimensions has renewed interest in ultra thin oxides. The desirable properties of ultra thin oxides for gate dielectric applications are: very low defect densities, low charge trapping characteristics and high break down voltages. Although the ultra thin oxides grown by wet oxidation technique have higher breakdown strengths compared to that of dry oxide, the wet oxide has invariably large trapping characteristics and has problems in uniformity and surface roughness. In the present investigation, the effect of water vapor pressure (0.004 - 1.0 atm) on the ultra thin oxides of silicon grown by wet oxidation technique has been attempted. The wet oxidation is carried out in a quartz furnace maintained at 800°C for 5 - 120 minutes. The ultra thin oxides are grown on single crystal CZ silicon wafers : n-type, (100) oriented, single side polished, of resistivity 1.0 - 10 Ωcm. The thickness of the grown oxides(3- 10 nm) has been estimated from the measured C-V characteristics and are also confirmed by ellipsometer measurements. The thickness of the oxide (60 minutes) seems to be rather independent at water vapor pressures till 0.05 atm. In order to understand the electrical performance of these thin oxides, Al/thin SiO2 / n-Si MOS structures are fabricated and their Capacitance (C ) - Voltage (V) (in the frequency range : 10 KHz - 1 MHz), conductance (G) - voltage (V) and Current (I) - Voltage (V) characteristics have been studied. Interface density (Dit) and fixed oxide charge density (Qf) have been evaluated to asses the quality of the thin oxide layer. The breakdown voltage and the charge trapping characteristics have also been studied. The results indicate that reproducible ultra thin oxides can be grown with sufficient control by wet oxidation technique at reduced water vapor pressure.
EM-WeP-5 Nanoscale Silicon Features Produced by Slow Highly Charged Ions
M.W. Newman, A.V. Hamza, H. Lee, A.V. Barnes, T. Schenkel, J.W. McDonald, G.A. Machicoane, T. Niedermayr, D.H. Schnieder (Lawrence Livermore National Laboratory)
Phase transformations induced by intense, ultrafast electronic excitation from slow highly charged ions from the Lawrence Livermore National Laboratory (LLNL) Electron Beam Ion Trap(EBIT) have been studied. A 308 keV beam of Xe44+ (~51 keV of potential energy) was used to irradiate a 3 mm spot of clean float zone (FZ) silicon (100) (2X1) for a total dose of ~5x1011 ions. Due to the indirect nature of its band gap, bulk silicon is typically a poor photon emitter upon external excitation. However, as the crystal size approaches nanometer scales, the band gap widens due to quantum confinement and becomes direct allowing for more efficient photon emission. Ex-situ room temperature photoluminescence (PL) spectra were measured using a high resolution grating spectrometer with an excitation wavelength of 379 nm from a Titanium-Sapphire laser. PL spectra from areas exposed to SHCI bombardment show a broad emission centered at 504 nm. This is consistent with emission observed from 1-2 nm silicon nanocrystals. No PL is observed from similarly prepared FZ Silicon samples exposed to beams of 308 keV Xe27+ (~10 keV of potential energy) and 5 keV Xe1+ with comparable doses. A series of sharp lines at 548 nm, 534 nm, and 530 nm are also present in the PL spectrum from areas exposed to Xe44+ which is characteristic of an excitonic series in nanometer size direct band gap materials. The deposition of potential energy from Xe44+ produces a phase transition in silicon surfaces at nanometer size level that is not produced from normal ion bombardment. This work was performed under the auspices of the U.S. Department of Energy by Lawrence Livermore National Laboratory under contract No, W-74505-ENG-48.
EM-WeP-6 Formation of Ni-silicides on (001)Si with a Thin Interposing Pt Layer
L.-W. Cheng, S.-L. Cheng, L.-J. Chen (National Tsing Hua University, Taiwan, R.O.C.)
As devices dimensions scale down to deep sub-micron regime, a linewidth dependence of sheet resistance was observe for TiSi2. Among metal silicides, low resistivity NiSi is currently one of the two most promising silicides to replace TiSi2 for the self-aligned technology of ULSI. NiSi possesses low resistivity, low silicon consumption, low processing temperature and relative insensitivity to the linewidth of the silicide. Previous works showed that the process window of NiSi can be extended to higher temperatures by nitrogen ion implantation. In the present work, the formation of Ni-silicides on (001)Si with a thin interposing Pt layer have investigated. TEM, XRD, SIMS and four point probe were used to analyze the characteristics of nickel silicide thin films. Pt addition was found to retard significantly the formation of nickel silicides on (001)Si. The process window of NiSi was extended to a higher temperature and the sheet resistance maintained the same low level in a wide temperature range. NiSi was observed to be the dominant phase for the samples annealed at 400-800 0C with a thin interposing Pt layer. Since nickel atoms are the dominant diffusing species in the Ni/Si binary system, the results implied that the diffusion of nickel atoms through Ni/Si interface is retarded by the presence of a thin interposing Pt layer.
EM-WeP-7 The Interfacial Reaction between Ti and (001)Si with an Interposed Mo Layer
S.-M. Chang, L.-J. Chen (National Tsing Hua University, Taiwan, R.O.C.)
Low resistivity TiSi2 has been widely used in ultralarge scale integrated circuits because it possesses the low resistivity and compatibility with the SALICIDE processing. However, as the devices dimension shrinks to the deep submicron regime, it becomes increasingly more difficult to use thermal annealing to transform a structure from the high resistivity C49 phase to the low resistivity C54 phase due to insufficient nucleation sites of C54 phase at the C49 phase grain boundaries. Recently, a new and simple method for the reduction in the C54 transformation temperature was demonstrated. The formation temperature of the C54 TiSi2 phase from the bilayer reaction of Ti on Si is lowered by about 100°C by placing an interfacial layer of Mo between Ti and Si. However, the detailed mechanism is still not well understood. In the present study, high-resolution transmission electron microscopy (HRTEM) was utilized to study the interfacial reaction between Ti and Si with an interposed molybdenum layer. A thin amorphous TiSix layer was found to form and a thin Mo5Si3 layer was formed at the interface between the Si substrate and amorphous interlayer after 500°C rapid thermal annealing (RTA) for 30 s. In addition, island formation was found to occur for Mo5Si3 after 535°C RTA for 30 s. C49-TiSi2 and Ti5Si4 phases were found to form simultaneously after 550°C RTA for 30 s. The growth rate of amorphous TiSix layer was delayed with the presence of metallic interfacial layer. The formation temperature of the C49 TiSi2 phase was also found to increase. The redistribution of Mo atoms, in the form of a ternary Ti-Mo-Si phase, after 550°C RTA for 30 s, leads to the enhancement of the formation of C54-TiSi2 by providing more heterogeneous sites needed for the transformation from C49- to C54-TiSi2 phase.
EM-WeP-8 Characterizing and Modeling the Electronic Conduction in CrB2-SiC-Si Thin Films
F. Wu (Medtronic, Inc.)
Characterizing and modeling the electronic conduction in CrB2-SiC-Si thin films The CrB2-SiC-Si material system is used in thin film resistors in very large scale integrated circuits application. The films are sputter deposited onto dielectric substrates from composite target using various reactive gas mixtures. The microstructure of the sputter deposited CrB2-SiC-Si films is characterized by TEM as a distribution of darker ‘island’ regions within an lighter ‘boundary’ medium. In a wide range from 10-3 to 103 ohm -cm, the film resistivity is found as a function of the CrB2, Si and N composition. A model is proposed in this paper and computer simulation is perform to model the film resistivity behavior.
EM-WeP-9 Silicon Nano-dots Fabricated on a Si(100) Surface via Thermal Nitridation and Oxygen Etching Reactions
J.S. Ha, K.-H. Park, W.S. Yun (ETRI, Republic of Korea)
We have fabricated silicon nano-dots with a very uniform size distribution on a Si(100) surface via a thermal nitridation followed by an oxygen etching reaction. Nitrogen gas was exposed to a clean Si(100) surface at 800 °C and this surface was subsequently reacted with O2 gas at 700 °C under an oxygen partial pressure of 1x10-7 Torr. Scanning tunneling microscope (STM) measurement of the surface morphology showed that silicon nano-dots with an average size of 5 nm were formed as a result of selective oxygen etching of silicon surface. It is considered that nanometer-scale silicon nitride islands worked successfully as masks for the oxygen exposure at high temperatures. The number density of silicon nano-dots is estimated to be 1 x 1012 / cm2. Reduction of the nitridation temperature to 700 °C resulted in the similar surface features with a little bit smaller sizes, indicating that silicon nitride islands formed even at this temperature can be successfully used as masks for oxygen exposure. Further investigation of the post-annealing effect on the resultant surface morphology showed that the coalescence of small sized silicon nitride islands into larger ones, which was clearly observed in the case of Si(111) surface, was not noticeable on the Si(100) surface. Therefore, uniform and small size distribution of Si nano-dots could be obtained on the Si(100) surface. In this paper, we will also discuss on the underlying reaction mechanisms based upon experimental results. This study suggests a simple but efficient fabrication method of silicon nano-dots using gas-surface reactions on the silicon surface in an ultra-high vacuum system.
Time Period WeP Sessions | Topic EM Sessions | Time Periods | Topics | AVS1999 Schedule